#milkymist IRC log for Tuesday, 2012-01-17

cladamwwpwrak, (VGA DDC failed :: 6 / 90) wpwrak, I'm thinking this problem...even you mentioned that intermittent problem, possibly12:11
cladamw caused by software.12:11
cladamwwpwrak, but i'm not sure and don't know if existing another potential reason, why i'm thinking this? since i reviewed R2 known issues and compared to R3 known issues about L3 and L19 shorted to fix frozen problem,  would it be also likely to "ground problem" to cause noises?12:11
cladamwwpwrak, you can see my http://lists.milkymist.org/pipermail/devel-milkymist.org/2011-March/001289.html12:12
cladamwseems that I'm editing DVI-I sch, so just thought up if this un-suitable 'ground' arrangement may cause DDC failed? not just only re-plug.12:15
cladamw(R4: DVI-I single link sch) http://downloads.qi-hardware.com/hardware/milkymist_one/sch/tmp/Milkymist%20One%20R4%20-%2020120117.pdf12:57
cladamwhot plug detect pin 16 on J17 hasn't been added.12:58
cladamwthe sch is not draft yet.13:00
wpwrakhmm, DDC indeed looks fishy17:09
wpwrakbut more in a "this can't work" way than in a "this sometimes doesn't work" way17:10
wpwraklekernel: what version of DDC does M1 implement ?17:10
larscthe one which uses i2c probably17:11
wpwrakthe hardwre looks DDC1-ish. wikipedia says "Very few display devices implemented this protocol."17:12
larscwhat makes you say so?17:12
wpwrakand I2C would need bidirectional SDA. unless i'm missing another instance of VGA_SDA, it's only an input17:13
wpwrakhmm. or maybe not17:13
larscwhy is it input only?17:14
wpwraknot sure what to make of that circuit. haven't seen such a thing17:14
larscthats a common thing on i2c busses17:14
larscis a level converter17:14
larscit is17:14
larscsome cheap trick, don't ask me how it works17:15
wpwrakbrr. gives me headache :) but maybe that's just from last night's party17:16
lekernelThe most common version, called DDC2B, is based on I²C, a serial bus17:20
lekernelthat's what we have17:20
lekerneland yes, the mosfet hack is a bidirectional level translator, which so far has always worked fine (except for that time when resistors weren't properly placed during production of course ...)17:21
wpwrakinteresting bug :)17:30
lekernelit's not a bug17:32
lekernelthe mosfet is operating within specs17:32
lekernelwhat it does is pull the other line low when the voltage drops to ground on one line17:33
wpwrakno, i mean improperly places resistors17:34
Action: larsc was just working with a board last week which had the same problem 17:37
wpwrakhmm, nothing calls vga_read_edid in FN. maybe time for another shell command. the more we can do from a "standard" FN environment, the better17:37
lekernelyeah, DDC is totally unsupported beyond dumping the EEPROM in the demo firmware and checking its header in the production test software17:38
wpwraklarsc: how many hours did that little issue cost the customers of your employer ?17:38
larscwpwrak: probably none. it's a xilinx board17:40
wpwrakso you knew the resistors were missing when you go it ?17:41
larschad to find it out the hard way17:41
larscbut luckily they weren't in the schematics either17:42
larscso it was quite obvious what was wrong17:42
lekernela xilinx devboard? which?17:44
larscml605 rev.d17:44
wolfspra1lwpwrak: do we have a final plan on the new u-shape expansion system header assignments?21:38
wolfspra1lI think now that J3 is solved and Adam is working through the schematics would be a good time to finalize the proposal, unless it happened already?21:38
wolfspra1lor are we waiting on a bit of pin counting to find out how many free pins even still exist on the fpga?21:39
wpwraki don't know where adam is with rearranging things. does he already have an idea how much space will be there ?21:40
wolfspra1lmy last understanding was that we change the J21 header to female. Does this mean we are also OK with changing the pin assignments of that connector? Or we still keep the same?21:40
wpwraki would keep it the same21:40
larschm, why do you want to change it to female?21:47
wolfspra1lthat was proposed because, lemme see21:49
wolfspra1la) easier to mechanically insert the daughterboard21:49
wolfspra1lb) more expensive part (mechanical connector) is on m1, making the daughterboard cheaper21:50
wolfspra1lc) less open pins sticking up from m1, creating shorting opportunities21:50
wolfspra1lthe downside of course is that we break compatibility with pre-R4 boards, which I felt about strongly, but seems at that point I was the only one21:51
wolfspra1lif we leave all pins the same, we at least have some degree of backwards compatibility because we can make or send around a small male-to-female adapter/cable21:51
wolfspra1lsorry b) was "more expensive part (female connector) is on m1"21:52
larschm, right now i'm using the j3 to interface with external peripherals using jumperwire21:52
wolfspra1lanything else but a-c ?21:52
larscbut ok21:53
wolfspra1lwpwrak: I think for the space we also in parallel need to specify what we want21:53
wolfspra1lspace can be created, in easier or harder ways21:54
wolfspra1lso I don't think Adam will have any opinion on space. his plan is to finalize schematics, and after review go to the layout folks and then worry about space.21:54
wpwrakwell, we can make a draft spec, as a guide for the direction things should take22:06
wolfspra1lI don't think we can finalize the R4 schematics before chinese new year, so we have a bit of time22:15
wpwrakalright. we can make the draft this week, then collect comments.22:41
wolfspra1lsure. I think from Adam's perspective, two things are still open: 1) J21/u-shape 2) leds22:46
wpwrakah yes, the leds22:48
wolfspra1lok, let's confirm with Adam tomorrow where the whole thing stands22:51
wolfspra1land then before Friday (his vacation), we need the overview on used and available pins22:52
wolfspra1lwith that data, we can finalize the expansion system and leds next week, without space considerations22:52
wolfspra1lthen when adam comes back we finish and review the schematics22:52
wolfspra1lafter that it goes to the layout house where space may come back, and we may have to remove a few things22:53
wolfspra1lthat's the process as I understand it right now...22:53
wolfspra1lfor the layout house, I think we remove the 8-layer pcb as an option (that was discussed at some point when we also thought about dvi dual-link)22:54
wolfspra1lso we first try to work with the 6-layer pcb constraint, and only if that fails miserably (after layout feedback), we would open that option up again22:55
wpwrakso still 6 layer. nicer (as long as things still fit)22:55
wolfspra1lwell I'm just describing the process, things go back and forth between a number of people22:55
wolfspra1lso there may always be surprises :-)22:55
wolfspra1lbut this sounds about right?22:55
wpwrakyeah, sounds good. but we should put some estimates for the space in the draft22:58
wolfspra1ldon't understand22:58
wpwrakthe J21 draft should indicate what dimensions we think it may/should have23:00
wolfspra1loh, I thought it's already clear that it's a 100mil female header?23:00
wolfspra1lsame as the current one, so 2*9 ?23:00
wpwrakah, but there's much more :)23:02
wolfspra1lI'm behind :-)23:03
wolfspra1lso then yes, we should specify that along with the schematics for the layout house23:03
wpwrakspace between the two headers. space available/reserved for the board. position of projection on the side wall. the current rating of the pins (e.g., copy & paste from xilinx docs)23:04
wpwrakand, related, placement of a hole for a spacer (for strain relief) on the main pcb23:05
wpwrak(strain) e.g., insertion pressure. wouldn't be so nice if the main pcb flexed and chips popped off23:05
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