#milkymist IRC log for Thursday, 2011-12-22

azonenbergr events01:28
cladamw( ultrasonic cleaner ), just tried to book the smt vendor who helped to produce the second run ( rc2 )of JTAG/Serial daughter board. Will know soon if I can go there.02:44
cladamwIt's great that they have that clean machine which minbo does not have. I hope they can let me to visit that machine.02:46
cladamwhttp://vicso.com.tw/02:49
wpwrakcladamw: sounds great !03:23
wpwrakcladamw: seems a little odd that minbo don't have such cleaning equipment. it's kinda essential ;-)03:24
cladamwwpwrak, the remaining three boards: one is at minbo site to remount fpga, the other two I'd like to use/try ultrasonic cleaner. I hoped they can help me even this rc3 was not mounted by them.03:31
wpwrakgood idea. then you'll also see if the board is "ultrasound-safe"03:33
wpwrakhow are the characteristics of vicso and minbo ? are vicso generally better equipped ?03:34
cladamwjust try then we know if can be survived and know which part will be impacted by ultrasonic wave.03:34
wpwrakyeah. in principle, it should be safe. but we'll see :)03:36
cladamwwpwrak, so far I didn't record visco's facilities. so don't know to compare via exact hard data.03:36
cladamwminbo is the one that i can easily enter their smt room or else. but for visco or weijei ( rc1 JTAG/Serial daughter board ) it's not easy. Always book and wait for a while then entering like you entered Customs.03:39
wpwrakah, i see. that's of course inconvenient03:39
cladamwthe more you dealt with them, the more easier to enter. :(03:40
wpwrakthey know how to create incentives ;-)03:43
cladamwwpwrak, could you point me the link of your KiCad footprint libarary?03:50
cladamwwpwrak, under http://projects.qi-hardware.com/index.php/p/kicad-libs/source/tree/master/ ?03:51
cladamwwpwrak, where's passive components or you created via KiCad's original ones ?03:52
wpwrakgrrr04:05
Action: wpwrak hates those disappearing acts04:05
wpwrakfir the logs, the answer would have been: http://projects.qi-hardware.com/index.php/p/kicad-libs/source/tree/master/modules/stdpass.fpd04:07
wpwrakand the *-M footprints exist only for historical reasons and should be ignored (they're identical to the non -M versions)04:08
mbufis there a RSS feed to track releases of milkymist software? in particular http://milkymist.org/socdist/05:44
cladamwgood, just made a book done on next Tuesday for using ultrasonic cleaner.08:29
wolfspraulwpwrak: I didn't fully understand your usb power switch mail08:35
wolfspraullast I unerstood was that connecting the i-creativ would reset your m1rc4 board08:35
wolfspraulthat doesn't sound good :-)08:35
wolfspraulbut that was without the power switch?08:36
wolfsprauland the power switch works or doesn't work?08:36
lekernelwpwrak: __set is only for object attributes, no?10:08
wpwrakwolfspraul: the i-creativ was with my old  M1rc3 reworked with the 4.0 V reset chip. (but without USB power switch)10:56
wpwrakwolfspraul: the power switch in M1pre-rc4 seems to offer partial protection. i think the i-creativ will be fine with it. it's a bit difficult to make non-synthetic tests because the usb receptacles don't have a good connection. tilt them a little and they disconnect from VBUS.10:58
wpwraklekernel: should only be attributes - unless there's more evil going on underneath i haven't figured out yet :)10:59
wolfspraulwpwrak: hmm11:01
wolfspraul:-)11:01
wolfspraulyou know I'm a skeptic reader. what does 'partial' mean? :-)11:02
wolfspraulI guess work is still ongoing...11:02
wolfspraulno rush11:02
wolfspraulthanks a lot for helping with this and testing and all! that is really great11:02
wpwrak(partial) means that, it i create a worst-case scenario of a straight short, then there's no hope of escaping a reset11:05
wpwraks/it/if/11:06
wpwrakhowever, if the USB thing is at least halfway civilized, it's probably okay. also excessive capacitative loads aren't as bad as a straight short11:07
wolfsprauland what does that mean in the bottom line?11:12
wolfspraulwhat is a 'good' design for m1?11:12
wolfspraulyou know it can never be perfect... we can just add more and more protection but make the actual design worse. have we find the perfect balance yet? or not sure yet?11:13
wpwraki think we'll find it "adequate"11:25
wpwrakmaybe we can move to monitoring the regulators derived from 5 V in the future. that would avoid spurious resets on USB upsets that don't affect internal operation of the M1.11:26
wpwrakthat would still leave the 5 V rail vulnerable to major upsets11:28
wpwrak(adequate) i.e., even the worse-case overcurrent insult (shorting) will not cause damage. but it will reset the M1.11:29
wpwrak(adequate) non-broken USB equipment, even if exceeding the specs in a bad way, will probably work. still need to check a few more things, though.11:30
wpwrak(more things) i.e., see how real-life loads perform. also, check that we don't drop too much voltage on the switch11:35
cladamwwpwrak, hi nice report ! one question about (over 3000 samples). how long does it take while measuring 3k samples? And time slot varies in reference to where?11:42
wpwrakthanks ! :) hmm, never measured how long it takes. let's see ... about two minutes ...11:52
wpwrakyeah, ~126 seconds11:54
wpwrakand the averaging was 1 PLC, not 10. corrected.11:55
wpwraki did the whole set of tests spread over something like 12 hours, so there are also some environmental variations in there11:55
cladamwmmm...so from the time happened of 'short' then started to count 3k in ~126 seconds? or count it but not include the period of 'short', right?11:56
cladamw40us vs 126 second, the result of samples should be still quite the same I guess. :)11:57
wpwrakah yes, the voltage measurements are in stable states. so either without short or permanently shorted11:59
wpwrakmy meter isn't fast enough to catch the drops in a short11:59
wpwrakat the fastest setting, i could measure at maybe ~1.25 kHz12:01
cladamwunderstood now. :)12:02
wpwraknaw, even less. about 300 Hz. way too slow :) only the scope helps there12:03
lekernelwhat does the verilog standard say for zero-length constants? e.g. $display("%b", {4'b1010, 0'b0});16:21
lekernelgplcver => 10100000000000000000000000000000000016:21
lekerneliverilog => 101016:21
lekernel...16:21
lars_interesting16:23
lars_it's probably not even legal by the standard ;)16:24
lars_or maybe it says undefined behaviour in which case the two implementations would be correct16:27
GitHub13[migen] sbourdeauducq pushed 3 new commits to master: https://github.com/milkymist/migen/compare/8a394f9...f0aac4b18:41
GitHub13[migen/master] corelogic: operator tree - Sebastien Bourdeauducq18:41
GitHub13[migen/master] csr: use optree - Sebastien Bourdeauducq18:41
GitHub13[migen/master] flow: actor class - Sebastien Bourdeauducq18:41
GitHub146[migen] sbourdeauducq pushed 3 new commits to master: https://github.com/milkymist/migen/compare/f0aac4b...1ce4fbd23:40
GitHub146[migen/master] fhdl: encapsulate replicated constants - Sebastien Bourdeauducq23:40
GitHub146[migen/master] flow: sum and division actors - Sebastien Bourdeauducq23:40
GitHub146[migen/master] example: flow conversion - Sebastien Bourdeauducq23:40
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