#milkymist IRC log for Sunday, 2011-12-18

wpwrakhmm. messy capitalizations. i wonder how long until you trip over them yourself :)00:17
wpwrakElif, Constant, ..00:17
lekernelthat's not messy00:18
lekernelit avoids clashing with the python reserved keywords00:18
wpwrakthat's what you may think now ;-)00:18
wpwrakyeah :)00:18
lekernelseems clear that "if" is the python if, and "If" is the FHDL statement00:18
wpwrakwhere did the code of uart.v move ?00:18
lekerneland the others are consistent00:18
lekernelto uart/__init__.py00:21
lekernelI'm trying to get rid of all the "self." but it resists00:22
lekernelthis works with python 2, but not with 3 ...00:23
wpwrakpython likes its "self" :)00:23
wpwrakgo you actually use python for more as a glue and for infrastructure here ?00:25
wpwraks/as/than as/00:25
wpwrakby shoehorning all this into python, you get a very cluttered syntax. tons of parentheses, etc., which aren't really necessary00:26
lekernelit's still not as bad as VHDL :-)00:26
wpwrakwould it be possible to do worse ? ;-)00:27
lekernelthe main source of clutter imo is the "self."00:28
lekernelparentheses are still ok, especially with indentation00:28
lekernelwe should have "self" only for signals that are accessed outside the object... internal signals should be on the get_fragment local scope00:29
wpwraki see mainly four problem areas: the self, having to avoid reserved words, the parentheses, and generally having to form a list00:30
lekernelhaving to form a list is fine, because you can generate it algorithmically too00:31
lekernelwhich can be quite powerful00:31
wpwrakmaybe a dedicated language could solve this in a considerably cleaner way. since the procedural part of the language would only execute at run time, code generation could be kept simple (you'd just "execute" the ast)00:31
wpwraks/run time/build time/00:32
lekernelthere's already the ast, only we manipulate it directly with the python syntax atm :p00:32
wpwrakyeah. python is where the problem is :)00:32
wpwrakthe idea of putting a higher-level language over one that lacks expressivity is sound. just fitting this into python makes it complicated00:33
wpwrakand why do you prefix all the signals names with underscores ? again keyword avoidance ?00:37
lekernelnot all, only internal signals (not meant to be accessed from other objects)00:37
lekernelas I said, those should be moved to the get_fragment local namespace (and the underscore unnecessary and removed)00:38
lekernelI can simply say "tx_busy = Signal()"00:40
lekernelbut the problem is that the Signal class then doesn't know the variable name, and generates an anonymous signal in the final Verilog00:40
lekernelit works, but can make the generated code difficult to understand00:40
lekerneltx_busy = Signal(name="tx_busy") also works, but is redundant00:40
wpwrakcan't you overload the assignment ? ;-)00:41
lekernela macro would be convenient here00:41
kristianpaulhmm, i tought code difficult to understand wasnt something to care about00:42
wpwrakkristianpaul: you mean "it's okay" or "it should be avoided" ?00:42
kristianpaulnot okay. no never :)00:42
kristianpaulbut anyway if the thing build a system.v in seconds..00:43
kristianpauls/care/dont care00:43
kristianpaulbut yeah hacking conbus is more messy..00:43
wpwrak(overload the assignment) i'd still get rid of python, though. what i usually do is make a few code examples and see what the "ideal" language would look like. then i implement it with lex and yacc and put cpp in front of it all. that way, i get includes, conditional compilation, macros, and also comments for free00:44
lekernelno but here, we also need python to generate complex structure procedurally00:45
wpwrak(cpp et al.) e.g., function load_file in http://projects.qi-hardware.com/index.php/p/fped/source/tree/master/fped.c00:45
lekernelthough a domain-specific language could still be useful, as an extra feature, for manual coding like the UART00:45
wpwrakand the cpp invocation here: http://projects.qi-hardware.com/index.php/p/fped/source/tree/master/cpp.h  (and cpp.c)00:45
wpwrakas long as you don't need much more than if, loops, maybe recursion, and basic variables, you can just do that on your domain-specific language. it's not very hard to make an interpreter.00:47
lekerneldo what?00:47
wpwrakmake procedural constructs like if (...) ... else ..., while (...) ..., etc.00:48
lekernelno but half the point of FHDL is that you can create constructs from anywhere in Python00:48
lekernelsee for example the round-robin arbiter example: https://github.com/milkymist/migen/blob/master/migen/corelogic/roundrobin.py00:49
lekerneland that's still a simple one, I want to build way more complex stuff later00:50
wpwrakyeah, but while it helps you get rid of semantical complexity, python adds substantial syntactical complexity.00:50
wpwrakand a for or if construct is entirely feasible in an interpreted customized language00:51
lekernelthe round-robin arbiter example generates nested ifs00:51
lekernelit's not a simple for/if construct00:51
wpwrakyou could probably even get rid of those "accumulators" (cases, comb, etc.)00:51
lekernelI see the point for modules that are manually coded, like the UART00:54
lekernelbut for generating procedural structures, they aren't bad00:54
wpwrakthe RR is a bit tricky indeed. there you have both languages working. if what they do would be completely orthogonal, then you would have no choice. but i don't think it is. lemme ponder this for a bit ...00:56
wpwraki guess recursion (in the "outer" language) should do the trick01:09
wpwrakwell, you can generalize that01:09
wpwraka "function" could be similar to a macro, only that some of the parameter evaluation happens as build time01:10
wpwrakthe return value would be a bit of verilog or modified verilog. you'd probably also want functions that can do math and such, which you could solve with the explicit return of a value. a function that tries to do both would be an error. (like in many other languages)01:12
wpwrakthen you'd just use that function inside the code, acting like a fancy macro01:13
wpwrakyou could extend this with a mechanism that allows you to put the code generated into a variable. e.g., foo = { <code>  } then you wouldn't even need recursion.01:23
wpwrakthere <code> could contain loops etc.01:23
wpwrakyou probably don't need full separation of name spaces. a common name space also makes the code easier to read, as long as the semantics aren't easily confused01:25
wpwrakthinking of it, you can probably use the same namespace for both languages. control constructs would just change their meaning depending on how you use them.02:37
wpwrakthis may seem hackish but it's not different from what compilers for languages as down to earth like C do02:38
wpwrake.g., if (<const>) -> resolve at build time02:39
wpwrakif (<expression-of-only-custom-language-vars>) -> also resolve at build time02:39
wpwrakif (<expression-of-only-lower-level-language-vars>) -> emit code02:40
wpwrakif (<mixed-expression>) -> emit code, replacing custom language vars with their respective value02:40
wpwrakin the end, you'd just have a self-optimizing super-verilog :)02:41
lekernelwpwrak: hmm, but in the end I'll need more complex stuff than the RR10:47
lekernelI'll probably end up building FHDL constructs with about every Python feature - and I do not want to reinvent the wheel...10:48
lekernelhow about a dumb preprocessor to smooth out the ugly syntax bits...?10:48
roh lekernel i sometimes wonder if it wouldnt be easier to have some processing or ardunino-esque language for patches11:44
roheasier to teach/understand for people11:44
rohlike.. have one 'init/setup' and one 'event demux main function' as a stub and let people hack from there11:45
wpwraklekernel: every problem in IT can be solved by adding yet another layer of abstraction ;-)12:15
wpwraklekernel: regarding every feature of python - once the language is turing-complete, you have no limits :)12:17
wpwrakroh: sections is what i'm after :)12:17
lekernelyes, so let's program this stuff in assembly, it's turing-complete too :)12:18
wpwrakroh: in fact, you have them right now. just the syntax is a bit unusual12:18
lekernelor even better, writing the CPU instructions manually in hex12:19
wpwrakah, the good old days ;-)12:19
wpwrakdon't forget that you still have all the power of C at your disposal to implement the primitives of that language. if you need really complex stuff but that's at least somewhat general, then you can just add a primitive. or make a kind of library.12:20
wpwrakalso, you'll never find a language that can do everything and still look sane12:22
wpwrakso if you need some really crazy stuff, you can always write a script that generates your "extra-high-level language"12:22
lekernelso far, the only problem I see with using the python interpreter for FHDL is slightly cluttered syntax12:27
lekernelit's minor, and there are ways to improve it, like a preprocessor12:27
lekernelfor the rest, it seems pretty powerful12:28
wpwrakoh, python can do a lot. it may get slow, but that's probably not an issue in this case12:30
wpwraki'd be more concerned about having a deep stack of translators12:30
lekernelthe stack is about as deep in the traditional parser -> AST vs. preprocessor -> python parser -> AST case12:31
wpwrakparticularly in the first ten years of that thing maturing, you'll constantly have to check things at all layers12:32
lekernelthe 2nd case is more powerful, and the preprocessor can easily be made optional12:32
lekernel(should it cause issues in some cases)12:32
wpwrakhmm, how do you like gcc's parse trees ? :-)12:33
wpwrakand how often do you use them ?12:33
wpwrakthe generated python would become just that - an intermediate language used understood by a vanishingly small minority of people12:34
wpwrakso the preprocessor is no longer optional12:34
lekernelremoving cluttering parentheses and redundancy in signal declarations doesn't look like a complex transform, does it?12:35
wpwrakyou also need to disentangle namespaces12:35
lekernelnope. everything happens in the python namespace.12:36
wpwrakand you may end up with a different scope structure12:36
wpwrakso anyone using the language needs to know not only the rules of that language itself, but also python to avoid python name collisions, plus verilog to avoid verilog name collisions ?12:37
lekernelverilog name collisions are already taken care of in the backend12:37
lekernelit automatically renames conflicting signals12:38
wpwrakfurthermore, if you don't have a full parser on top, you get cryptic error messages from the layers below12:38
lekernelthe language itself is python with some optional syntactic sugar based on trivial macro expansions12:38
lekernelthat's all12:38
wpwrakthen you probably still miss a lot of potential for syntactical simplicity12:39
lekernelnothing's for free. and it's already a step forward from VHDL in this respect...12:40
wpwrakyou could try this: pick a simple but not trivial piece of verilog, then write it down how you'd wish you could write it with verilog, i.e., staying close to the original structure, but getting rid of clutter and with access to constructs that reduce redundancy. then see if a language pattern emerges12:41
lekernelas I said: half the point of FHDL is to be able to use all that python provide to generate complex structures12:41
lekernelyou'd miss that with a brand new language, and/or reinvent lots of wheels12:42
wpwrakwhat sort of python features do you expect to need for these complex structures ?12:44
lekernelclasses, dynamic typing, maybe libraries so you can pre-compute things like filter coefficients for DSP easily12:45
wpwrakdynamic typing is easy. classes are harder (but rarely necessary). the occasional numbercrunching can be done outside, like where you use scilab to generate a table. (forgot what it was)12:47
wpwrakin fact, when i look at how many people use classes (i.e., each problem is solved by adding more of them, until you get these thickets that can only be traversed with an IDE), i'd say not having them is a good thing ;-)12:53
lekernelfor the dataflow system I'm planning, I'll pretty much need classes - or at least, records12:58
lekerneljust look at how much mess there is in the TMU to pass current pixel information from one pipeline stage to the next12:58
wpwrakrecords are basically a syntactical variant of generalized arrays12:59
wpwrakso if you have generalized (= index can be of any time) arrays, you're good13:00
wpwrakyou could probably rip most from my umlsim language ;-)) (which actually happens to have classes)13:01
lekernelnow I want a generic component that buffers (FIFO-style, and with configurable size) whatever records are fed to it13:01
wpwrakyou get that with dynamic typing. and does the size even have to be limited ?13:02
lekernelyes, because that component has to be translated to Verilog and synthesized13:03
lekernelyou don't have unlimited on-chip storage13:03
lekerneland by the way, we may want that FIFO to be able to grow automatically a DMA port to move the storage off-chip13:03
lekernelof course, that DMA port will then be semi-automatically connected to the appropriate bus in the SoC13:04
wpwrakbut would there also be records that get buffered in m1gen ? or would you just have a structure that says there is a fifo but don't populate it with data in m1gen ?13:05
lekernelmigen doesn't run anything... it's just a verilog translator13:05
wpwrakso what you;re looking for is something that says "fifo-structure", plus a type that defines what goes inside13:06
wpwrakand the size limit for verilog13:06
lekernel"hardware" thingies like TLM and System-C, which run everything in a simulator but can't synthesize a thing, are merely only good for writing PhDs13:06
lekerneland yes13:07
lekernelthat's exactly what the FIFO component should do13:07
wpwrakwell, you said yourself that you want to do number-crunching and that you need "about every Python feature" :)13:08
lekerneland it should provide a function that manipulates the FHDL to implement the FIFO functionality13:08
wpwrakmanipulates .. in what way ?13:09
lekernelgenerate a "fragment" that can be combined with the rest of the system13:10
wpwraka module ? or part of a module ? or an ensemble of modules ?13:11
lekernelyes, that's close to what Verilog calls a "module"13:11
wpwrakthe "combining" would then mean that it's placed in the same hierarchy. i.e., not that it would go and do substitutions in the rest of the verilog ? e.g., to place accessors13:16
lekernelatm FHDL generates a completely flattened hierarchy, but maybe I'll implement some heuristics in the back-end to make the generated code more readable by splitting it into Verilog modules13:17
wpwrakah, i see13:17
lekernelbut I want to make the Verilog hierarchy completely transparent from the FHDL user's point of view13:17
wpwrakat what point do xilinx' tools choke anyway ? ;-))13:17
lekernelI don't think they do... I've done more horrible things to them13:18
wpwrak"FATAL ERROR: maximum module size 64 kB) exceeded" ;-)13:18
lekernellike synthesizing the full LM32 for a different FPGA, translating the netlist back into Verilog, doing some hand tweaking of the file to make it synthesizable, and replace the original LM32 with that netlist written in Verilog and instantiating LUTs/flip-flops/etc. directly13:19
lekernelthat was to track down a difficult synthesizer bug ...13:19
lekerneliirc the Verilog file was several MB13:20
wpwrakokay, so you'd so something like:  my_fifo = new fifo(size, type); ... my_fifo->push(foo); ... bar = my_fifo->pop();   ?  or, equivalent, my_fifo = fifo_new(size, type); ... fifo_push(my_fifo, foo); ... bar = fifo_pop(my_fifo, bar); ...13:20
wpwrakgood. so no file size limit :)13:21
lekernelno, the FIFO will be part of a data flow graph13:21
wpwrakah, i see13:21
lekernelfifo.connect_input_stream(foo);  fifo.connect_output_stream(bar);13:21
wpwrak"foo" and "bar" would be "fragments" ? or some sort of endpoints ? or both ?13:32
lekernelno, endpoints13:32
lekernelbut that'll be part of the dataflow system which I have not started coding, so don't look for this yet :)13:33
wpwrakokay, so you'd declare the endpoints, then do  something(foo)  in a "fragment" when you want to access the data ?13:34
lekernela class declares endpoints13:35
lekernelthe same class produces a fragment that implements its functionality13:35
lekernelthe dataflow system connects endpoints together13:35
lekernelthe dataflow system can generate another fragment that implements the endpoint interconnect13:35
wpwrakbtw, i'm not sure "fragment" is a good word. it means a part of something that was whole before it got broken. those code snippets work just in the opposite direction: they are fused to build a whole13:36
stekernlekernel: it sounds like you want systemverilog, but dys in python :P13:36
lekernelstekern: systemverilog isn't synthesizable13:36
stekernI know13:36
stekernI wish it was13:36
lekernelso it has near zero interest for me13:36
lekernelnon-synthesizable "hardware" is only for PhD-ware lurking in the darkness in some academic institution and spending 90% of their time writing grant applications13:37
wpwrak(dataflow) okay, but how will the endpoint be accessed ? e.g., if i have a uart-rx and i just got a nice new byte in "shifter". how do i send it into the fifo at endpoint "foo" ?13:38
lekernelthere will be a formal exchange protocol, similar to what is currently implemented between TMU pipeline stages13:39
wpwraknaw, phds don't spend on average quite so much time writing applications ;)13:39
lekernelbasically, strobe_out, ack_in for outputs13:39
wpwrakthat's open-coded or would there be some wrapper ?13:40
lekerneland strobe_in, ack_out for inputs/sinks13:40
lekernelthat would depend on the "scheduling model" of that component13:40
lekernelthere will be predefined scheduling models for common behaviours, such as a fixed-latency pipeline, or a sequential unit that produces its result after a fixed number of cycles13:41
lekernelthe exchange signals would be autogenerated for those, and the dataflow system would also try to remove completely those exchange signals and replace them with static scheduling and a FSM13:42
lekernelbut for more complex cases, you can also go for the dynamic scheduling model that lets you deal directly with those signals (and disable the dataflow system optimizations)13:42
wpwraki mean just the endpoint access. i guess you could have "blocking" and "non-blocking" there. though they may end up being the same, with "it's still busy" translating to "error/ignore" in one case and "go something/defer" in the other13:42
wolfspraulif a hardware description language is non-synthesizable, what's the point?13:43
wolfsprauldoesn't that make it a pure software thing?13:43
wolfspraulor is it meant to anticipate future advances in what is manufacturable?13:43
lekernelwolfspraul: writing PhDs and doing test benches13:43
wolfspraul(synthesizable I mean)13:43
lekernelthose are the main applications of TLM, SystemVerilog and SystemC13:44
wpwrakwolfspraul: it could still be useful for testing certain model properties13:44
wolfspraulsure, but it's pure software then, and due do it not being synthesizable (ever?) it cannot become hardware, right?13:44
wpwrakwolfspraul: e.g., the Spin language is, afaik, not used for code (or whatever) generation.13:44
wpwrakerr. sprry, promela. spin is the model checker13:44
wolfsprauloh sure, I understand. it's just not hardware then, and I guess never (?)13:44
wpwrakthat would depend on language characteristics. in theory, everything is synthesizable. in practice, you'd draw a line somwhere :)13:46
stekernwell AFAIK systemverilog wasn't solely designed for verification (as systemc is), it just hasn't caught on13:52
wolfspraulok but I was surprised about terminology13:54
wolfspraulhow can a 'hardware description language' be non-synthesizable?13:54
wolfspraulit then describes a theoretical hardware, I guess13:54
stekernwell it's describing hardware, but only for simulation purposes13:54
wolfspraulyes, so by definition that hardware can never be hardware, no?13:55
lekernelyou'd be surprised what design committees and academia are capable of doing ;)13:55
wolfspraulI'm just surprised about terminology, that's all. I'm learning.13:55
wolfspraulmaybe hardware includes 'theoretical hardware' - as long as everybody knows that so be it...13:55
wpwrakwell, if that's their goal, their time is limited, and nobody takes over after them, ...13:55
lekerneland yes - 'theoretical hardware' ...13:56
wpwrakthe problem with academia is that many a phd project ends abruptly once that phd has been awarded. the problem of industrial committees is that their horrid designs often do see the light of day :-)13:58
wolfspraulbut isn't it highly confusing that a 'hardware description language' is capable of describing something that cannot become hardware?13:59
wpwrakthat would depend on what exactly the "hardware" in there constitutes. could range from "it simply hasn't been implemented" to "we incorporate features and constraints typically found in hardware"14:00
wpwrakthere's also the issue of which subset of the language you'd actually consider synthesizing. and which subset of the chip's feature set you'd use.14:01
wpwrakmake each too small and it becomes pointless14:01
wpwrakmake each too big and you're crushed by complexity14:02
wpwrakand then, some languages have the problem that some of their properties just don't make sense. so the usable subset is extracted and then extended. pascal was a nice example for that ;-)14:03
lars_wpwrak: for the young folks among us: which properties of pascal didn't make sense?14:47
wolfspraulwell it's a good thing for me to learn anyway14:49
wolfspraulthat 'hardware' description language may well describe something that cannot exist in hardware :-)14:49
wpwrakstrings, the i/o subsystem, for larger projects the lack of separate compilation, then of course operator precedence14:51
wpwrakwolfspraul: i don't think it's like that. most likely, there simply is no direct way from the description to, say, verilog14:51
wpwrakwolfspraul: of course, at the extremes, you will always find that you can code something that cannot be implemented. be it in verilog, c, whatever.14:52
wpwraklars_: you still see the pascal bug of operator precedence when people write, in C, things like  ((foo == 1) || (bar == 2))  instead of simply  (foo == 1 || bar == 2)14:57
wpwrakin pascal, these parentheses were indeed needed. then people who grew up with pascal moved to C, without bothering to properly learn the language. so they still wrote things in pascal style. and then others, learning from example, copied that ...14:58
wpwrakanother bad things pascal was at least partially responsible of is the shunning of multiple exit points in loops and functions. pascal has "goto" but the use of that was maligned at that time. and it didn't have more structured mechanisms, like "break", "continue", or "return" (except the implicit one at the end of the function)15:02
wpwrakso people wrote code that had endlessly nested ifs. If precondition1 Then If precondition2 Then If precondition3 Then finally-to-the-thing; Else error3; Else error2; Else error1;15:04
wpwraksince the only exit was at the end of that function, you could never be quite sure nothing else would happen in a given branch, unless you checked all the way to the very end15:05
wpwrakand of course, if there was something else to do after that monster if, you'd set a boolean that basically said "skip all the rest" and then put ifs around all the other things15:05
wpwraksimilar for doing the equivalent of "break". it was then  While real-condition And Not getmeoutofhere Do Begin stuff If error Then getmeoutofhere := True; ... If Not getmeoutofhere Then ...; End15:07
wpwrakall very messy15:07
lars_and people used this?15:09
wpwrakyou mean the construct or the language ?15:13
lars_the language ;)15:15
wpwrakoh yes. it was extremely popular as an educational language (for forcing you to program "properly") and then also as a language for PC-class machines (CP/M 80, then PC-DOS, etc.)15:17
wpwrakit was competing with BASIC at that time. many implementations of BASIC didn't have any WHILE or such. just GOTO. you can imagine what that did in a language aimed at beginners :)15:18
wpwrak(beginners) e.g., all the "home computers" came with BASIC. in the 1980es, borland made turbo pascal. it ran on CP/M80 and it was *fast*. not necessarily the code it generated (i.e., i once wrote a compiler that did better), but the compilation speed was breathtaking15:19
wpwrakin that era, compilers were heavy and slow beasts15:19
wpwrakand C compilers for CP/M were either prohibitively expensive or barely usable. sometimes both.15:20
lars_i see15:41
Action: kristianpaul learn turboc back in college15:44
wpwrakturbo c came long after turbo pascal15:45
wpwrakalso, ms-dos didn't have virtual memory, so it was very easy to crash the system with bad pointers (that's an issue less common in pascal)15:46
wpwrakof course, the meme that languages like C, which give you fairly free use of pointers are therefore dangerous probably comes from that era15:47
wpwrakalready with an MMU, you catch most pointer issues. and for the last decade or so we've had tools like valgrind that get rid of the remaining problems as well15:48
wpwraktoday, the main risk are programs with buggy code paths that aren't visited in testing. of course, there are tools for avoiding that as well ...15:49
kristianpaulyou mean like python? in wich still the risk hidden bugs as there is no compilation at all15:50
wpwrakyeah. some of the "safe" languages like python have this sort of trap. talk about replacing one problem with another :)15:51
kristianpaulgood point15:53
lars_so the logical conclusion is to use managed code at kernel level and use unmanaged code for userspace applications15:54
wpwrak"managed code" ?15:56
kristianpaulyes, what does mean?15:56
kristianpaulnon interpreted?15:56
lars_it's what microsoft calls languages like c#15:57
wpwrakand what would be unmanaged then ?15:58
wpwraknaw, C is fine for everything. in the kernel you need massive reviews anyway.15:59
lars_which are often not done16:00
kristianpauleverything, yay !16:00
wpwrakin linux ? well, in general it is. perhaps not perfectly all the time, but people do have a look16:01
kristianpaulrtems counts as kernel btw?16:01
wpwrakthere you have an example of weak reviews. they're using regression tests, which is a good idea, but they don't seem to have good coverage16:03
lars_i've become a big fan of coccinelle recently16:03
wpwrak"... was a French transsexual actress"  ?16:05
lars_the other one16:06
kristianpaulacording to wikipedia yes16:06
kristianpaul"French word for ladybug" *g*16:06
lars_semantic patching16:07
wpwrakah, 3rd one :)16:07
lars_allows you catch all that stupid mistakes which are done over and over again16:08
lars_and also automatically generates a patch to fix the issue16:08
wpwraki see how it can help with (automated) fixing. how does it help with "catching" ?16:11
kristianpaulgarh, my jtag pod is getting loose agaib :|16:12
lars_wpwrak: e.g. http://web.mornfall.net/repos/linux-2.6/git/scripts/coccinelle/null/deref_null.cocci finds code where a pointer is dereferenced before it is checked for NULL16:12
lars_foo->bar = 10; ... if(!foo) ...16:13
wpwrakaaah, nice16:13
lars_or for example there is patch which finds users of GFP_KERNEL where GFP_ATOMIC should have been used16:14
wpwrakthat NULL pointer check could actually go into gcc :)16:15
wpwrak"warning; de facto constant expression" :-)16:15
lars_i've mainly been using coccinelle for automated refactoring. e.g. changing a functions signature. it's much nicer than grep and sed16:18
lars_or replacing open coded versions of macros or functions16:18
lars_it's good for people like me who are a bit OCDish with code style issues sometimes.16:24
wpwrakhehe ;-) so i guess coccinelle is good at observing proper indentation16:25
lars_it can do that too16:25
lars_but what i meant was e.g. using const for things which should be const16:26
wpwrakthat's tricky to identify, though16:26
wpwrakwell, you could automate it. tentatively add a "const" at the first place where there could be one, adapt all the callers, see if you get errors/warnings. if yes, don't do const. if no, keep it. then proceed with the next.16:28
lars_if you know that a function takes a const parameter16:29
lars_you can find all calls to this function and check whether the variable which is passed as the parameter is ever modified. if not make it const16:30
wpwrakcoccinelle can find such thing ? wow16:31
wpwrakthat's pretty complex. does the code have to be -Wshadow-clean ?16:31
wpwrakand does it see what goes on in macros ?16:31
lars_well, if you include the macro defintion yes16:32
wpwrake.g., #define POKE(p) (*(p) = 0)16:32
lars_but by default includes are not followed16:32
lars_because it increases execution time quite a bit16:32
wpwrakyeah, i can imagine16:40
wpwrak(NOR) passed 10'000. this time with a full check (including non-fatal corruption, which i forgot the last time).17:59
lekernelgreat! and thanks for the tests!18:04
wpwrakyeah, i think it's time to schedule the last rites for the bug ;)18:05
kristianpaulawesome :)18:17
GitHub154[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/41e2430e2b3759b70fd406947ec9365c3ffcefc020:31
GitHub154[migen/master] fhdl: automatic signal name from assignment - Sebastien Bourdeauducq20:31
lekerneldirty, but got it to work =]20:31
lars_dirty indeed. if all objects which gets signals assigned were of a certain base class you can override __setattr__20:38
lekernelI also want to declare local signals in functions, and there isn't any way to do this with py3k (except with a preprocessor, which is also quite messy)20:43
lars_may you can modify locals() __setattr__ ;)20:51
GitHub175[migen] sbourdeauducq pushed 2 new commits to master: https://github.com/milkymist/migen/compare/41e2430...107f03f20:52
GitHub175[migen/master] fhdl: also take into account object attributes in _make_signal_name. Get rid of declare_signal - Sebastien Bourdeauducq20:52
GitHub175[migen/master] Remove uses of declare_signal - Sebastien Bourdeauducq20:52
lekernelnope... the locals are analyzed at compile-time with py3k20:52
GitHub95[migen] sbourdeauducq pushed 3 new commits to master: https://github.com/milkymist/migen/compare/107f03f...af0a03b20:59
GitHub95[migen/master] fhdl: better matching of assignment - Sebastien Bourdeauducq20:59
GitHub95[migen/master] corelogic: fix signal exports - Sebastien Bourdeauducq20:59
GitHub95[migen/master] examples: remove old-style declarations - Sebastien Bourdeauducq20:59
GitHub111[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/D627_g21:06
GitHub111[milkymist-ng/master] Use new syntax - Sebastien Bourdeauducq21:06
lekernelwpwrak: still seems too cluttered for you? https://github.com/milkymist/milkymist-ng/blob/master/milkymist/uart/__init__.py21:06
lekernelthe original verilog is within this https://github.com/milkymist/milkymist/blob/master/cores/uart/rtl/uart_transceiver.v21:07
lekerneland https://github.com/milkymist/milkymist/blob/master/cores/uart/rtl/uart_transceiver.v#L3821:08
lekernelend of march 2012 in Amsterdam... can probably make it21:29
kristianpaullooks very nice event  for what M1 cant miss a space21:44
kristianpaulalso feedbacks, seems from pictures people assinting can suguest features for M1 *g*21:52
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