| wpwrak | yup | 00:03 |
|---|---|---|
| wpwrak | NOR is on 3.3 V. fpga core on the 1.x V (one or both, too lazy to look it up :) | 00:05 |
| whitequark | I "like" how the isim happily eats incorrect syntax and produces undefined behavior | 01:05 |
| whitequark | is this feature intended to taunt lazy engineers?.. | 01:05 |
| whitequark | also, simulating a reset edge concurrently with a clock edge is NOT a good idea. | 01:10 |
| whitequark | gah | 01:28 |
| whitequark | I just made a processor with branch delay slot, which is at exactly PC(branch) + 3 position | 01:29 |
| lekernel | whitequark: your reset, like the rest, should be synchronous | 11:12 |
| lekernel | they are many examples of designs with asynchronous resets (featuring strongly, of course, at the #1 community within broken IP-cores), but they do not map well to modern FPGAs and can cause metastability if you are not careful | 11:14 |
| GitHub115 | [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/ec4739401270bf0ad09360a0d00bbc29d250b3e3 | 14:03 |
| GitHub115 | [migen/master] verilog: support for float parameters in instances - Sebastien Bourdeauducq | 14:03 |
| GitHub193 | [milkymist-ng] sbourdeauducq pushed 2 new commits to master: http://git.io/ZPjt9Q | 14:04 |
| GitHub193 | [milkymist-ng/master] clkfx module - Sebastien Bourdeauducq | 14:04 |
| GitHub193 | [milkymist-ng/master] Multiply system clock - Sebastien Bourdeauducq | 14:04 |
| GitHub36 | [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/6f8a6db40a64df0272daf25979d8dbe6fa984ce8 | 14:24 |
| GitHub36 | [migen/master] verilog: get the simulator to run the combinatorial process at the beginning - Sebastien Bourdeauducq | 14:24 |
| GitHub18 | [milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/d6Iw2A | 14:26 |
| GitHub18 | [milkymist-ng/master] norflash tb: use get_fragment - Sebastien Bourdeauducq | 14:26 |
| GitHub170 | [milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/xlCq0w | 14:59 |
| GitHub170 | [milkymist-ng/master] 32-device, 8-bit CSR bus - Sebastien Bourdeauducq | 14:59 |
| GitHub166 | [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/1a845d45539662a78347f765cc6aa986ad728745 | 14:59 |
| GitHub166 | [migen/master] 32-device, 8-bit CSR bus - Sebastien Bourdeauducq | 14:59 |
| whitequark | lekernel: I meant the simulation | 15:33 |
| whitequark | i.e. always #20 clk <= ~clk; initial reset = 1; #20; reset = 0; | 15:33 |
| wpwrak | wolfspraul: first round of NOR torture: if the bug was still there, it would have caused a corruption with a probability of 99.92%. but no corruption was evident. | 15:40 |
| wpwrak | wolfspraul: one more day of testing will add an extra safety margin of a factor of about 1000 | 15:41 |
| krispaul | csr_addr = 5 finally :) | 16:23 |
| GitHub4 | [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/d21e095397ebbe45757cbaf06385878f3670062d | 19:36 |
| GitHub4 | [migen/master] fhdl: fix series of if/elif/else - Sebastien Bourdeauducq | 19:36 |
| GitHub156 | [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/135a2eb86899149d9877202600877577a6445983 | 23:32 |
| GitHub156 | [migen/master] bank: support raw registers - Sebastien Bourdeauducq | 23:32 |
| GitHub156 | [milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/KMYTBw | 23:34 |
| GitHub156 | [milkymist-ng/master] uart: new design using FHDL and bank (TX only, incomplete) - Sebastien Bourdeauducq | 23:34 |
| --- Sun Dec 18 2011 | 00:00 | |
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