#milkymist IRC log for Wednesday, 2011-12-14

cladamwxiangfu, the lastest boot.crc.d41c1c9.bin can't enter selection in test program. http://pastebin.com/Wd11fDdQ01:41
cladamwxiangfu, but I think that you're working on it.01:41
xiangfucladamw, not finish yet.01:41
xiangfuyes. working on that.01:42
xiangfuyou can use 'boot.bin' for test.01:42
cladamwxiangfu, http://milkymist.org/updates/2011-11-29/for-rc3/ so you will update here soon?01:43
xiangfuI will delete the boot.crc.d41c1c9.bin now.01:43
cladamwokay...I/m going to use that latest 'boot.bin', tks!01:44
cladamwyes. the test.bin works well except crc item. :-)01:56
xiangfuthere must some detail I missed.02:01
xiangfuI skip 72bit in linker.ld BSS section.02:02
xiangfuappend the CRC to the end of the file.02:02
whitequarkhere is my brainfuck softcore: http://pastie.org/301359002:21
whitequarkit synthesizes (to 128 slices on spartan-3e), but is untested yet02:21
cladamwxiangfu, sorry that I didn't test midi item. The midi item doesn't work. I guess this is caused by midi low level f/w or fpga codes changed.03:14
xiangfumidi item. I will check that.03:29
whitequarkit even kind of works! http://rghost.ru/34637451.view03:54
whitequarknah. hangs at loops :/04:15
wolfspraulwpwrak: wow great, that's a relief [customs]04:43
wolfspraulhow much did you have to pay? did the invoice help?04:44
wolfspraulwhy was it kicked out of the standard process?04:44
wolfspraulwpwrak: oh I got your mail about customs - great05:04
whitequarkit works! http://rghost.ru/34642301.view06:01
whitequarkand here is the CPU itself: http://pastie.org/301424306:02
whitequarkkristianpaul: can you insult my code? :)06:03
kristianpaulwhitequark: why i'll do such thing?11:17
wpwrakwolfspraul: i had to pay USD 124 in customs fees. that's a bit higher than usual - normally, it's 50% of declared value with EMS or regular mail, and a little lower with fedex. maybe they calculated the fees over value plus shipping, which would actually be the "official" formula.11:48
wpwrakwolfspraul: plus USD 37 for storage.11:48
wpwrakwolfspraul: so all more or less within the expected range.11:49
wolfspraulok good12:34
wpwrakwolfspraul: how's .de ? busy pimping M1 already ?12:47
lekernel.de ?13:10
lekernelbtw - finally (!) demoing M1 to Peter tomorrow :)13:10
wpwraklekernel: (.de) wolfgang is in germany now13:21
wpwrakpeter ... gabriel ?13:22
ThihiHmm, btw. nobody answered me here the other day. Are there other variables in the flickernoise patch script language that use the video input in some way except the video_a variable?13:24
wpwrakhmm, seems to be the only one (haven't done much with video yet)13:25
lekernelThihi: yes, it's the only one so far13:32
lekernelwolfspraul: where? let's have a beer if you're not too far from Berlin :)13:33
whitequarkkristianpaul: well, it was an unusual way to ask for code review.15:14
kristianpauli dont feel like a persona to ask those thins, i'm prety to this, also i had to learn on the road15:15
kristianpaulbut i will insisnt in jump directly to milkymist code hacking15:16
whitequarkI don't have an M115:22
kristianpauli dont meant that, milkymist code is free you dont need a M1, also very portable15:24
kristianpaullike the tdc-core at the cern open hardware repository, very portable implementation15:24
whitequarkwhat do you think I can do now?15:25
whitequarki.e. what in the code needs fixing and not needs an M115:27
kristianpaullearn :)15:27
kristianpaulwell if you really interested15:28
whitequarkkristianpaul: that's what I'm doing now:)15:32
whitequarkI think the next try will be a pipelined bf CPU, just to understand the implications15:35
whitequark(I don't actually think I can modify something in lm32 code and make it work. it's quite complex)15:35
kristianpaulwhitequark: Fallenou did some blog entry in his blog about the topic15:36
kristianpaulwhitequark: check pfu core, is part of my and therotically easy to customize15:37
lekernellm32 isn't complex15:39
kristianpaulbut worth to customize?15:39
whitequarklekernel: it isn't. but I have 1 (one) day of fpga experience15:40
kristianpauli remenber was just one or two extra isntrucionts that can be added?15:40
whitequarkkristianpaul: can you link to his blog? I can't google it15:42
kristianpaulYann Sionneau15:58
kristianpaulmilkymist blog fpga15:58
whitequarkah yes, found it now16:00
whitequarkquite interesting16:01
lekernelbtw, I'll be speaking at http://www.notacon.org/16:24
whitequarkokay, I don't understand this16:30
whitequarklook, I have a RAM block which is driven, as far as I understand, by a positive clock edge16:31
whitequarkthere exists a design, where three things happen simultaneously16:31
whitequarka) positive EN positive16:31
whitequarkb) address change16:31
whitequarkc) positive clk edge16:31
whitequarkafter one full clk cycle, the data appears, and looks like that it works stable16:32
whitequarkbut this is clearly a setup time violation16:32
whitequarkisn't it?16:32
whitequark*a) positive EN edge16:32
whitequarkthe RAM is a standard Xilinx Spartan3E BRAM16:32
lekernelhm... you should read some courses on synchronous logic systems16:33
lekerneland use synchronous logic as much as possible, the s3e architecture is made for that16:33
whitequarklekernel: that design is synchronous16:36
whitequarkstill: am I wrong?16:36
stekernwhere are they happening, in the waveform in simulations?16:37
lekernelwhat is EN exactly? the block RAM CE?16:38
lekernelthat pin is synchronous, and has setup/hold constraint wrt the clock signal16:38
whitequarkstekern: it works both in simulation and on a real board16:38
lekernel(often automatically enforced/checked by the tools)16:38
whitequarklekernel: https://github.com/grindars/bfcore/blob/master/IRAM.v16:38
whitequarkthe BRAM is generated automagically by XST16:38
lekernelyes, it's block RAM CE16:39
lekernelso A and EN have to stay stable a fraction of a nanosecond before the clock edge, and a fraction of a nanosecond after the clock edge16:40
lekernelmost often, the tools take care of this for you16:40
whitequark(waveforms: http://rghost.ru/34731201.view)16:40
whitequarkso, the XST (or PAR?) is clever enough to insert some internal delay to comply to setup/hold time constraint?16:41
lekernelgenerally the hold time is granted, because the flip-flops actually switch a short while after the clock edge16:42
lekernelPAR, however, does try hard to maintain the setup time (which determines the maximum clock frequency of the circuit)16:43
stekernwhitequark: I thought you were asking about not seeing that fraction of a nanosecond lekernel spoke about in simulations16:46
lekernelsimulations use delta-delays, which is something else16:47
whitequarkstekern: that too16:48
whitequarkI have just read about setup/hold time constraints, and I've seen how it works both in simulation and in a real device16:48
whitequarkwhile, in my opinion, it should have not16:48
lekernelwhitequark: when simulating a synchronous circuit using an event-driven simulator, you should rely on the delta-delay algorithm, not insert delays in your code16:49
lekernelmany people do not understand delta-delays and go for the latter option (even in some organizations where you would expect to see skilled designers), and this is a typical *HDL code smell16:50
stekernyeah, delays in the code sucks16:54
lekernelwell, at least those people understand synchronous circuits. I remember an epic PS/2 controller from Potsdam university... I should grab the code and post it somewhere as an example of what not to do =]16:55
kristianpaulyes please :)16:56
GitHub8[milkymist] sbourdeauducq pushed 5 new commits to master: https://github.com/milkymist/milkymist/compare/6f50e96...14a31d417:15
GitHub8[milkymist/master] milkymist: remove unused variables in libbase/softfloat.c - Werner Almesberger17:15
GitHub8[milkymist/master] milkymist: use -Wstrict-prototypes - Werner Almesberger17:15
GitHub8[milkymist/master] milkymist: try -Wmissing-prototypes - Werner Almesberger17:15
GitHub4[flickernoise] sbourdeauducq pushed 1 new commit to master: http://git.io/ZdOP5w17:16
GitHub4[flickernoise/master] parser_helper.c: use asprintf instead of DIY solution - Werner Almesberger17:16
wpwrakis the MIDI test cable a regular MIDI cable or does it have some special features ?17:18
lekernelwpwrak: why are you returning const char * in fpvm_parse? it's a dynamically allocated string ...17:19
lekernelregular MIDI cable17:19
wpwrak(const char *) because the recipient isn't supposed to change it.17:20
lekernelmh... if you want... but then you have to cast it when passing to free()17:22
wpwrakyes, i do that17:22
lekernelC's "const" is broken anyway... use as you would use someone else's toothbrush17:22
lekernelyeah, but it's more typing17:22
wpwrakheh :) yes, "const" is a bit quirky. and i don't like it that "free" needs casts. but it helps in all the other places where such a string may be used.17:23
GitHub76[flickernoise] sbourdeauducq pushed 1 new commit to master: http://git.io/tYEw_g17:23
GitHub76[flickernoise/master] ptest: fix memory leak - Sebastien Bourdeauducq17:23
lekernelanother detail is it's a little confusing to name stuff in FN with a "fpvm_" prefix17:24
wpwrakyes ... most of that can go anyway. just a question of cleaning up a little more17:25
wpwraki kept fpvm_ because some thing are from there, so i didn't have to change the callers. since then, i've eliminated most of the callers :)17:26
wpwrakhmm. autotest is unhappy. hates my midi :-(17:26
wpwrakthere are a few other things, like the comments ending up in infra-fnp.h, the "_xy" variable, adding things like per_vertex to the name table. little details that slow things down.17:28
lekernelwpwrak: maybe the autotest doesn't support mwalle's new UART core?17:29
lekernelso you plan to remove parser_helper?17:29
wpwrakbut for now my goal is functionality. then the cleanup. there are a few more things that want cleaning up anyway, like the symbol lookups17:29
wpwrak(parse_helper) haven't consider that yet. i think it has its uses.17:30
lekernelwell, all it contains is fpvm_parse and fpvm_parse_free you said you would remove17:30
wpwrak(UART core) hmm, could be. there were a lot of interrupt changes as well, weren't there ?17:31
wpwrakah, i was thinking of the things in fpvm.c17:32
wpwrakfpvm_parse* only need a renaming :)17:32
wpwrak(uart) maybe i'll leave this to you then :) you already know what to change.17:33
lekernelyes, i'll have a look17:33
lekernelyou see I'm doing efforts to support Linux :) easier Linux support was the main motivation for the new UART17:34
wpwrakhehe, great :)17:35
wpwrakthe usb test is funny. asks to press enter/left button on port A then on port B. but you can just do both on the same port ;-)17:35
wpwrakof course, there's no way to tell anyway, at that level :)17:36
GitHub108[autotest-m1] sbourdeauducq pushed 1 new commit to master: http://git.io/59j1xg17:45
GitHub108[autotest-m1/master] Remove dependency on libmath - Sebastien Bourdeauducq17:45
GitHub15[milkymist] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/milkymist/commit/14ad8baf3a5d3a2cc01698ff3439e5e2894f2f9317:47
GitHub15[milkymist/master] Remove libmath - Sebastien Bourdeauducq17:47
wpwrakhehe, die libmath, die ! ;-)17:48
wpwrakso we just haev softfloat to produce lots of complains with -Wmissing-prototypes not17:50
lekerneland the autotest17:50
wpwrakyes, i've seen some function() there as well. haven't tried to crank up the warnings over there yet, though17:51
whitequarklekernel: I have another question then18:04
whitequarkxilinx docs say that BRAM works on _both_ edges18:04
whitequarkthen, can I first latch in an address in a manner described above18:05
whitequarkand then wait for 1/2 of clock cycle and disable CE?18:05
whitequarkoutput buffers should still be active, and I'll be able to make a second request in a very next clock cycle18:05
whitequarklike this:18:16
whitequarkCLK  _|>|_|>|_|>|_|>|_|>18:16
whitequarkCE   _|>>>|___|>>>|___|>18:16
whitequarkA    _X___X___X___X___X_18:16
whitequarkD    <_1_X_2_X_3_X_4_18:16
whitequarkREG  <_1_X_2_X_3_X_18:17
whitequarkCE should have been = CLK.18:18
whitequarkand freenode ate my precious combining unicode.18:19
juliusbi'm not sure if IRC is the best medium for waveform viewing18:50
whitequarkjuliusb: well, I've been drawing these ones... for a while and didn't want to throw them out.18:51
whitequarkotoh, they are still meaningful.18:51
mwallelekernel: is autotest the production test suite?18:57
whitequarkTI: "Your device is a product of superior design and craftsmanship and should be treated with care."20:03
whitequarkhave they ever heard of modesty? :D20:03
whitequark(after that, they suggest that I should "Do not attempt to open the device.20:04
whitequarkwell, it's fine, except for the fact they are describing a PCB.20:04
whitequarkalso, since when PCBs have "moving parts"?..20:05
wolfsprauljuliusb: why is irc not good for waveforms? I think those are awesome! whitequark - more plase :-)20:10
whitequarkwolfspraul: I'm thinking about releasing a library for drawing (awesome) unicode waveforms20:11
whitequarka "library"20:12
wolfspraulwe need to get more beginners into this scene, and we know it's a worthwhile endeavor so we can build bridges wholeheartedly20:12
wolfspraulit's not a fad that will go away in a year or two20:13
whitequarkwhat I see in Russia is a horrible, horrible lack of sensible engineers20:13
mumptaiand drawing waveforms will help?20:13
wolfsprauldiscussing about them, definitely imho20:13
whitequarkespecially young ones (< 50 yrs.), because old-schoolers, at least here, often prefer... suboptimal methods20:13
wolfsprauland discussion may be eased with a drawing :-)20:14
whitequarkso it would be very good if it actually worked.20:14
kristianpauli agree with wolfspraul , the ascii waves are not bad20:14
wolfspraulwhen I saw them I was first taken aback, but that's cool. new idea! waveform ascii art in irc - cool! :-)20:14
kristianpaulof course the link to a vcd file download is not bad either :)20:15
wolfspraulhow useful we find out over time20:15
Action: whitequark goes back to writing a pipelined brainfuck cpu core with branch prediction20:17
wpwrakroh: hmm, using http://projects.qi-hardware.com/index.php/p/m1/source/tree/master/cad/protocase_v7_laser.dxf, how can i tell what is engraving (text) and what is a cut through the board ?21:27
whitequarklooking at RTL makes me feel quite stupid.21:45
whitequarkcan I assume that a trigger has an implicit delay inside, and if several ones are connected in a sequence, a clock pulse _first_ latches the state of output to the input of next one, and _then_ switches the output?21:46
lars_more or less21:51
lars_but it all happens at the same time. so not "first" and "then"21:52
whitequarkwell, it happens at the same time for each of the individual flip-flops, yes21:53
whitequarkwhat I don't understand21:54
whitequarkif it happens _really_ at the same time21:54
whitequarkthen you cannot build a working chain of flip-flops at all21:54
whitequarkthey all will switch simultaneously21:54
lars_there is propagation delay21:54
whitequarkthat's what I have asked21:55
whitequarkwithout propagation delay, synchronous circuits cannot work, can they?21:55
lars_probably not21:57
lars_at least not the way we expect them to work21:57
whitequarkthanks, I understand the idea now21:58
whitequarklooking at RTL really helps to understand how the circuit you've just designed really works22:01
whitequarkor maybe I'm just fooled by C-look-alike-ness of verilog22:01
lars_do you use a lot of blocking statements?22:03
whitequarklars_: none of them22:04
whitequarkkristianpaul: hm?22:05
kristianpaulnon blocking way go, i agree with sebastien22:05
kristianpaulalso use as much you can always statements22:06
kristianpaullife easier :)22:06
whitequarkyes, I've already notices that22:06
lars_i fully agree. i never use blocking statements22:06
whitequarkif I put everything in one always statement, XST tends to infer some monstrosity22:06
whitequarkand if I don't, then it's a nice clean set of primitives as they should be22:07
lars_but imo non blocking is already quite close to rtl22:08
whitequarkblocking statements look quite foreign to FPGA's for me. they hide some internal state and tend to generate suboptimal code22:08
whitequarklars_: maybe that's just how my brain works: if it sees C-like text, it thinks procedurally, and if a circuit, then in a proper way22:08
whitequarkjust guessing22:08
whitequarkbut the thing I'm doing now had not started to work until I stared for 30 minutes at RTL.22:09
whitequarkthe logic was completely wrong22:10
lekernelwhitequark: no, BRAMs do not work on both edges. what they probably mean is you can select between reacting to rising or falling edges.23:04
lekernelbut you can't do both23:04
lekernelif you want to have 1 request per cycle, you can pipeline them23:04
lekernelbut keep everything synchronous... no half-cycles or things like that23:04
whitequarklekernel: I'm pipelining everything23:05
lekernelFPGAs aren't made for this, and it's a source of bugs and time wastage23:05
whitequarkand yes, everything I do is only done @(posedge clk)23:05
whitequarkbut I've thought of a "clever trick" for RAM access23:05
whitequark  assign ram_ce = should_fetch && clk;23:06
whitequarkINTERNAL_ERROR:Xst:cmain.c:3464:1.56 -23:07
whitequark(not related to the ram_ce)23:07
lekerneloh, and yes, if you try asynchronous designs, this tickles synthesizer bugs as well :-)23:07
lekernelclk should be connected *only* to clock ports23:07
whitequarklekernel: ah okay, then it is possibly related.23:08
whitequarkmaybe there is a clock gate23:08
whitequarkprimitive I mean23:08
lekernelI told you to do a synchronous design23:09
lekernelforget about clock gating23:09
lekernelthe FPGA architecture is optimized for synchronous designs, and the tools expect synchronous designs23:10
whitequarkthen I don't understand how one can get one request per cycle23:12
lekernelby presenting a new address after each clock edge23:12
whitequarkahh, so it does not need CE edges23:12
whitequarkyes indeed it does not. stupid23:12
lekerneland yes, this means that the data pins have the values from the previous address. that's where pipeline hazards and other niceties come from :-P23:13
whitequarkyeah. I've read See MIPS Run several times23:13
lekernelCE is a synchronous pin that tells it to read the new address when it's high23:14
whitequarkMIPS is a horribly bad processor design, but the book describes a lot of interesting things about processor internals23:14
lekernelits purpose is to _disable_ the RAM read for some cycles23:14
whitequarkstill "INTERNAL+ERROR"23:15
whitequarklekernel: can you take a look at my code? it just dies somewhere in the parser23:18
whitequarkwith a double free.23:18
lekernelmwalle: yes, autotest is the production test software23:19
whitequarkokay. an undocumented xst option -use_new_parser yes fixes that.23:37
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