| GitHub171 | [scripts] xiangfu pushed 3 new commits to master: http://git.io/ehBOdA | 04:02 |
|---|---|---|
| GitHub171 | [scripts/master] reflash_m1.sh use only one fjmem, cleanup - Xiangfu Liu | 04:02 |
| GitHub171 | [scripts/master] reflash_m1.sh update to latest release for rc3 - Xiangfu Liu | 04:02 |
| GitHub171 | [scripts/master] reflash_m1.sh bump version - Xiangfu Liu | 04:02 |
| GitHub3 | [autotest-m1] xiangfu pushed 1 new commit to master: http://git.io/sMe-YA | 05:19 |
| GitHub3 | [autotest-m1/master] fix typo, should use libmath.a - Xiangfu Liu | 05:19 |
| barbu-uucp | azonenberg: you might like this http://raintown.org/lava/ | 11:02 |
| azonenberg | "These pages assume a good understanding of Xilinx's Virtex FPGA architecture and of the Haskell lazy functional programming language. The number of people that know about both can easily fit inside a medium sized elevator" | 11:03 |
| azonenberg | Looks interesting but i question whether it's too complex to be of any use lol | 11:06 |
| barbu-uucp | you find it complex? | 11:08 |
| azonenberg | I understand what they're doing | 11:08 |
| barbu-uucp | it's not any worse than your pipelined adder :) | 11:08 |
| azonenberg | i just think that often you dont care about placement | 11:08 |
| azonenberg | But OTOH, mixing that with verilog or vhdl | 11:08 |
| azonenberg | for the most speed critical parts of the circuit | 11:08 |
| azonenberg | Might well be worth doing | 11:08 |
| barbu-uucp | what could be cool would be a high-level placer | 11:08 |
| barbu-uucp | something that operates on top of lava and automatically generates the lava-level placement constraints | 11:08 |
| azonenberg | HmmI definitely want to play with it, thats for sure | 11:09 |
| azonenberg | Is there a back end for spartan chips? | 11:09 |
| barbu-uucp | though lava itself already has a good deal of functions that generate placements | 11:09 |
| barbu-uucp | so it's not _that_ bad :) | 11:09 |
| barbu-uucp | no, I don't think so. you'd have to write it :) | 11:09 |
| barbu-uucp | some things have changed, e.g. the carry chains are more complex now | 11:10 |
| azonenberg | yeah | 11:10 |
| barbu-uucp | and 6-LUT architectures can build efficient ternary adders with one chain | 11:10 |
| barbu-uucp | so the adder tree example needs some revamping | 11:10 |
| azonenberg | Well, i am definitely going to fool around with it though | 11:10 |
| azonenberg | As well as manually doing low level (LUT and CLB based) FPGA dev at some point | 11:11 |
| azonenberg | I intend to learn the architecture inside out | 11:11 |
| barbu-uucp | azonenberg: you can also try to combine Lava with a DIY router (not too hard to do using the XDL descriptions) and the Recobus bitstream generator | 11:11 |
| barbu-uucp | lava to bitstream in 100ms, without any xilinx tool :) | 11:12 |
| azonenberg | lol | 11:12 |
| azonenberg | I do want a free toolhain | 11:12 |
| azonenberg | And one optimized for extreme performance wouldn't hurt | 11:12 |
| azonenberg | Something to look into when i have free time, perhaps | 11:12 |
| azonenberg | But I have a doctoral thesis in *computer science* to finish first | 11:13 |
| azonenberg | Maybe then i can think about doing one in EE :p | 11:13 |
| barbu-uucp | I wonder how hard it would be to run Haskell on the LM32 | 11:14 |
| barbu-uucp | cpython is messy, lots of dynamic code loading | 11:14 |
| barbu-uucp | ruby is super easy | 11:14 |
| azonenberg | No idea, i havent used lm32 | 11:15 |
| azonenberg | I'm actually writing my own softcore optimized for my specific workloads | 11:15 |
| azonenberg | 2-way superscalar barrel processor | 11:16 |
| azonenberg | 16 threads, it issues two instructions from each one in a round-robin fashion | 11:16 |
| azonenberg | then goes back and issues two from the first thread again etc | 11:16 |
| azonenberg | that allows a 16-stage pipeline with no stalls | 11:16 |
| barbu-uucp | well, the problem is actually not LM32 itself, it's more about the operating systems | 11:16 |
| azonenberg | in reality some of the FPU is 32 stages so i need to have one delay slot in which you can't use the output of the fdiv/fsqrt or it'll stall | 11:17 |
| barbu-uucp | python happily calls dl*() all over the place, that neither RTEMS or Linux implements properly | 11:17 |
| azonenberg | lol | 11:17 |
| azonenberg | I havent even started to think about the OS i'd run on this guy | 11:17 |
| azonenberg | But it'd have to be hardware multithreading aware | 11:17 |
| azonenberg | My roommate says that lava looks like the C of HDLs | 11:23 |
| azonenberg | as in, getting close to the architecture for maximum performance | 11:24 |
| azonenberg | while still maintaining some level of abstraction for ease of development | 11:24 |
| GitHub185 | [migen] sbourdeauducq pushed 2 new commits to master: https://github.com/milkymist/migen/compare/0ea7a9b...c840848 | 13:13 |
| GitHub185 | [migen/master] wishbone: decoder: fix slave cyc generation in registered mode - Sebastien Bourdeauducq | 13:13 |
| GitHub185 | [migen/master] verilog: use blocking assignment in combinatorial process - Sebastien Bourdeauducq | 13:13 |
| GitHub167 | [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/6f7a35e0a34a35cb1779e0e214aafce142ddbbd7 | 13:15 |
| GitHub167 | [migen/master] examples: Wishbone interconnect test bench - Sebastien Bourdeauducq | 13:15 |
| GitHub110 | [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/22d03b4943a3bb6339c03a0607c0893410766609 | 14:30 |
| GitHub110 | [migen/master] timeline: only trigger in rest state - Sebastien Bourdeauducq | 14:30 |
| lekernel | grmbl... icarus verilog is still incapable of simulating lm32 | 15:14 |
| stekern | really? why's that? | 15:18 |
| lekernel | it uses tons of macros and generate statements, and this confuses iverilog's little brain | 15:20 |
| stekern | I see | 15:21 |
| stekern | I haven't noticed any major issues with iverilog and generate statements, but maybe it's just particular ones that it gets confused by :) | 15:22 |
| lekernel | I can't get my migen-built soc to work, and the absence of a suitable simulator doesn't help | 15:23 |
| lekernel | maybe I should get a cracked modelsim ... | 15:23 |
| lekernel | or maybe xilinx isim would do the trick... I haven't tried it yet | 15:23 |
| stekern | it's slow as hell if you don't have the payed license and your design is larger than 'blink-a-led' | 15:27 |
| stekern | *paid | 15:29 |
| lekernel | well I just want to fix this one annoying bug | 15:35 |
| lekernel | ERROR:HDLCompiler:1654 - "../verilog/lm32/lm32_multiplier_spartan6.v" Line 47: Instantiating <D1> from unknown module <DSP48A1> | 15:39 |
| lekernel | phew | 15:39 |
| lekernel | "Using glbl as top_name is mandatory if behavioral design instantiates UNISIM primitiv es" ..... | 15:40 |
| lekernel | yay! got it to work! | 16:11 |
| kristianpaul | good, what was it? :) | 16:11 |
| lekernel | a stupid bug in the flash controller | 16:12 |
| lekernel | it would still use the address of the 1st request when 2 wishbone requests were sent without any "dead time" | 16:12 |
| kristianpaul | btw this m1gen will support multilple lm32 cores;) ? | 16:32 |
| lekernel | https://github.com/milkymist/milkymist-ng/blob/master/top.py | 16:38 |
| lekernel | if you add a parameter to the LM32 core that gives an "ID number" to each core, and if you don't need cache coherency, yes, it's easy | 16:39 |
| stekern | lekernel: that looks pretty nifty | 16:40 |
| GitHub18 | [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/929cc9807020ebaba3c1a6a77e786f5a8160c962 | 16:43 |
| GitHub18 | [migen/master] wishbone2csr: wait for WB deack - Sebastien Bourdeauducq | 16:43 |
| whitequark | hmm | 16:46 |
| whitequark | I guess I need to have ise webpack to do any work on MM core? | 16:46 |
| lekernel | what is "MM core"? | 16:47 |
| whitequark | the firmware of FPGA | 16:48 |
| whitequark | ise webpack license is like an agreement with satan | 18:58 |
| lekernel | whitequark: just write a replacement then | 19:00 |
| whitequark | lekernel: I'm not complaining | 19:01 |
| kristianpaul | mm/milkymist but is not a core is a SoC :) | 19:21 |
| whitequark | I don't understand almost anything in fpga world. | 19:22 |
| whitequark | can anyone say what do I need to do to get maybe a simulated lm32 core or whatever? | 19:22 |
| kristianpaul | fpga4fun is a good start, plus getting a m1 :) | 19:22 |
| whitequark | well | 19:22 |
| whitequark | $500 isn't something I can spend right now | 19:22 |
| kristianpaul | whitequark: you can run qemu for soft | 19:23 |
| whitequark | kristianpaul: I know how software works, thanks :) | 19:23 |
| kristianpaul | *g* | 19:23 |
| whitequark | wolfspraul expects me to write MMU for LM32. | 19:23 |
| whitequark | well | 19:23 |
| whitequark | he is quite optimistic then | 19:23 |
| whitequark | but still | 19:23 |
| kristianpaul | :) | 19:24 |
| n0carri3r | hey all | 19:25 |
| n0carri3r | just stopping by.. curious about the MIDIUSB :) | 19:26 |
| kristianpaul | hi | 19:26 |
| n0carri3r | hi | 19:26 |
| whitequark | is milkymist-ng the repository I should use? | 19:26 |
| whitequark | it's created 6 hours ago, hmm | 19:26 |
| kristianpaul | he dont think so, not yet tought | 19:27 |
| kristianpaul | just milkymsit whitequark | 19:27 |
| whitequark | kristianpaul: ah okay. I think I'll start with fpga4fun first | 19:28 |
| kristianpaul | whitequark: check this http://www.xess.com/appnotes/FpgasNowWhatBook.pdf | 19:29 |
| whitequark | a friend offers to lend me a nexys2 | 19:31 |
| whitequark | I guess it's fine for tutorials | 19:31 |
| kristianpaul | yes | 19:39 |
| kristianpaul | also for porting M1 to it | 19:40 |
| n0carri3r | gotta run bbiab | 19:44 |
| whitequark | kristianpaul: huh? it does not have any of m1 peripherals | 19:48 |
| kristianpaul | a FPGA | 19:50 |
| whitequark | kristianpaul: I'm not sure what do you mean... | 19:54 |
| wpwrak | good news: i liberated my pre-rc4 from customs | 20:20 |
| stekern | well, it's free hardware after all :P | 20:23 |
| whitequark | wpwrak: I wonder if that's an euphemism like "eliminate" | 20:26 |
| whitequark | are they still alive? (I hope no, but...) | 20:26 |
| wpwrak | well, today it wasn't too bad. only about 3 hours from arrival to departure | 20:30 |
| wpwrak | and no surprise costs | 20:30 |
| kristianpaul | wpwrak: congrats ! | 20:32 |
| kristianpaul | no adidional feeds either? | 20:32 |
| kristianpaul | whitequark: to get started you dont need a fully capable board | 20:33 |
| kristianpaul | just and fpga you can program and a serial port | 20:33 |
| whitequark | kristianpaul: well, I've relocated recently | 20:35 |
| whitequark | I don't even have a soldering iron. almost nothing, actually | 20:35 |
| whitequark | not even a single atmega :) | 20:35 |
| whitequark | so I | 20:35 |
| whitequark | *I'm thinking what can I get the cheapest and quickiest way | 20:35 |
| kristianpaul | you said you borrowed a nexsys2 dont you? | 20:37 |
| whitequark | not yet | 20:45 |
| whitequark | it's 00:45 here... | 20:45 |
| whitequark | 15 minutes more, and there will be no working public transport | 20:46 |
| whitequark | kristianpaul: okay. I've read several tutorials (including the NowWhat!?) | 23:07 |
| whitequark | and assembled something that works in simulator | 23:07 |
| whitequark | I think I'm starting to get the idea of how this stuff works. | 23:07 |
| mwalle | lekernel: btw pep8 defines function names to be lower_case_with_underscores() | 23:39 |
| whitequark | sigh. python. | 23:40 |
| --- Wed Dec 14 2011 | 00:00 | |
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