#milkymist IRC log for Tuesday, 2011-12-13

GitHub171[scripts] xiangfu pushed 3 new commits to master: http://git.io/ehBOdA04:02
GitHub171[scripts/master] reflash_m1.sh use only one fjmem, cleanup - Xiangfu Liu04:02
GitHub171[scripts/master] reflash_m1.sh update to latest release for rc3 - Xiangfu Liu04:02
GitHub171[scripts/master] reflash_m1.sh bump version - Xiangfu Liu04:02
GitHub3[autotest-m1] xiangfu pushed 1 new commit to master: http://git.io/sMe-YA05:19
GitHub3[autotest-m1/master] fix typo, should use libmath.a - Xiangfu Liu05:19
barbu-uucpazonenberg: you might like this http://raintown.org/lava/11:02
azonenberg"These pages assume a good understanding of Xilinx's Virtex FPGA architecture and of the Haskell lazy functional  programming language. The number of people that know about both can easily fit  inside a medium sized elevator"11:03
azonenbergLooks interesting but i question whether it's too complex to be of any use lol11:06
barbu-uucpyou find it complex?11:08
azonenbergI understand what they're doing11:08
barbu-uucpit's not any worse than your pipelined adder :)11:08
azonenbergi just think that often you dont care about placement11:08
azonenbergBut OTOH, mixing that with verilog or vhdl11:08
azonenbergfor the most speed critical parts of the circuit11:08
azonenbergMight well be worth doing11:08
barbu-uucpwhat could be cool would be a high-level placer11:08
barbu-uucpsomething that operates on top of lava and automatically generates the lava-level placement constraints11:08
azonenbergHmmI definitely want to play with it, thats for sure11:09
azonenbergIs there a back end for spartan chips?11:09
barbu-uucpthough lava itself already has a good deal of functions that generate placements11:09
barbu-uucpso it's not _that_ bad :)11:09
barbu-uucpno, I don't think so. you'd have to write it :)11:09
barbu-uucpsome things have changed, e.g. the carry chains are more complex now11:10
azonenbergyeah11:10
barbu-uucpand 6-LUT architectures can build efficient ternary adders with one chain11:10
barbu-uucpso the adder tree example needs some revamping11:10
azonenbergWell, i am definitely going to fool around with it though11:10
azonenbergAs well as manually doing low level (LUT and CLB based) FPGA dev at some point11:11
azonenbergI intend to learn the architecture inside out11:11
barbu-uucpazonenberg: you can also try to combine Lava with a DIY router (not too hard to do using the XDL descriptions) and the Recobus bitstream generator11:11
barbu-uucplava to bitstream in 100ms, without any xilinx tool :)11:12
azonenberglol11:12
azonenbergI do want a free toolhain11:12
azonenbergAnd one optimized for extreme performance wouldn't hurt11:12
azonenbergSomething to look into when i have free time, perhaps11:12
azonenbergBut I have a doctoral thesis in *computer science* to finish first11:13
azonenbergMaybe then i can think about doing one in EE :p11:13
barbu-uucpI wonder how hard it would be to run Haskell on the LM3211:14
barbu-uucpcpython is messy, lots of dynamic code loading11:14
barbu-uucpruby is super easy11:14
azonenbergNo idea, i havent used lm3211:15
azonenbergI'm actually writing my own softcore optimized for my specific workloads11:15
azonenberg2-way superscalar barrel processor11:16
azonenberg16 threads, it issues two instructions from each one in a round-robin fashion11:16
azonenbergthen goes back and issues two from the first thread again etc11:16
azonenbergthat allows a 16-stage pipeline with no stalls11:16
barbu-uucpwell, the problem is actually not LM32 itself, it's more about the operating systems11:16
azonenbergin reality some of the FPU is 32 stages so i need to have one delay slot in which you can't use the output of the fdiv/fsqrt or it'll stall11:17
barbu-uucppython happily calls dl*() all over the place, that neither RTEMS or Linux implements properly11:17
azonenberglol11:17
azonenbergI havent even started to think about the OS i'd run on this guy11:17
azonenbergBut it'd have to be hardware multithreading aware11:17
azonenbergMy roommate says that lava looks like the C of HDLs11:23
azonenbergas in, getting close to the architecture for maximum performance11:24
azonenbergwhile still maintaining some level of abstraction for ease of development11:24
GitHub185[migen] sbourdeauducq pushed 2 new commits to master: https://github.com/milkymist/migen/compare/0ea7a9b...c84084813:13
GitHub185[migen/master] wishbone: decoder: fix slave cyc generation in registered mode - Sebastien Bourdeauducq13:13
GitHub185[migen/master] verilog: use blocking assignment in combinatorial process - Sebastien Bourdeauducq13:13
GitHub167[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/6f7a35e0a34a35cb1779e0e214aafce142ddbbd713:15
GitHub167[migen/master] examples: Wishbone interconnect test bench - Sebastien Bourdeauducq13:15
GitHub110[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/22d03b4943a3bb6339c03a0607c089341076660914:30
GitHub110[migen/master] timeline: only trigger in rest state - Sebastien Bourdeauducq14:30
lekernelgrmbl... icarus verilog is still incapable of simulating lm3215:14
stekernreally? why's that?15:18
lekernelit uses tons of macros and generate statements, and this confuses iverilog's little brain15:20
stekernI see15:21
stekernI haven't noticed any major issues with iverilog and generate statements, but maybe it's just particular ones that it gets confused by :)15:22
lekernelI can't get my migen-built soc to work, and the absence of a suitable simulator doesn't help15:23
lekernelmaybe I should get a cracked modelsim ...15:23
lekernelor maybe xilinx isim would do the trick... I haven't tried it yet15:23
stekernit's slow as hell if you don't have the payed license and your design is larger than 'blink-a-led'15:27
stekern*paid15:29
lekernelwell I just want to fix this one annoying bug15:35
lekernelERROR:HDLCompiler:1654 - "../verilog/lm32/lm32_multiplier_spartan6.v" Line 47: Instantiating <D1> from unknown module <DSP48A1>15:39
lekernelphew15:39
lekernel"Using glbl as top_name is mandatory if behavioral design instantiates UNISIM primitiv es" .....15:40
lekernelyay! got it to work!16:11
kristianpaulgood, what was it? :)16:11
lekernela stupid bug in the flash controller16:12
lekernelit would still use the address of the 1st request when 2 wishbone requests were sent without any "dead time"16:12
kristianpaulbtw this m1gen will support multilple lm32 cores;) ?16:32
lekernelhttps://github.com/milkymist/milkymist-ng/blob/master/top.py16:38
lekernelif you add a parameter to the LM32 core that gives an "ID number" to each core, and if you don't need cache coherency, yes, it's easy16:39
stekernlekernel: that looks pretty nifty16:40
GitHub18[migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/929cc9807020ebaba3c1a6a77e786f5a8160c96216:43
GitHub18[migen/master] wishbone2csr: wait for WB deack - Sebastien Bourdeauducq16:43
whitequarkhmm16:46
whitequarkI guess I need to have ise webpack to do any work on MM core?16:46
lekernelwhat is "MM core"?16:47
whitequarkthe firmware of FPGA16:48
whitequarkise webpack license is like an agreement with satan18:58
lekernelwhitequark: just write a replacement then19:00
whitequarklekernel: I'm not complaining19:01
kristianpaulmm/milkymist but is not a core is a SoC :)19:21
whitequarkI don't understand almost anything in fpga world.19:22
whitequarkcan anyone say what do I need to do to get maybe a simulated lm32 core or whatever?19:22
kristianpaulfpga4fun is a good start, plus getting a m1 :)19:22
whitequarkwell19:22
whitequark$500 isn't something I can spend right now19:22
kristianpaulwhitequark: you can run qemu for soft19:23
whitequarkkristianpaul: I know how software works, thanks :)19:23
kristianpaul*g*19:23
whitequarkwolfspraul expects me to write MMU for LM32.19:23
whitequarkwell19:23
whitequarkhe is quite optimistic then19:23
whitequarkbut still19:23
kristianpaul:)19:24
n0carri3rhey all19:25
n0carri3rjust stopping by.. curious about the MIDIUSB :)19:26
kristianpaulhi19:26
n0carri3rhi19:26
whitequarkis milkymist-ng the repository I should use?19:26
whitequarkit's created 6 hours ago, hmm19:26
kristianpaulhe dont think so, not yet tought19:27
kristianpauljust milkymsit whitequark19:27
whitequarkkristianpaul: ah okay. I think I'll start with fpga4fun first19:28
kristianpaulwhitequark: check this http://www.xess.com/appnotes/FpgasNowWhatBook.pdf19:29
whitequarka friend offers to lend me a nexys219:31
whitequarkI guess it's fine for tutorials19:31
kristianpaulyes19:39
kristianpaulalso for porting M1 to it19:40
n0carri3rgotta run bbiab19:44
whitequarkkristianpaul: huh? it does not have any of m1 peripherals19:48
kristianpaula FPGA19:50
whitequarkkristianpaul: I'm not sure what do you mean...19:54
wpwrakgood news: i liberated my pre-rc4 from customs20:20
stekernwell, it's free hardware after all :P20:23
whitequarkwpwrak: I wonder if that's an euphemism like "eliminate"20:26
whitequarkare they still alive? (I hope no, but...)20:26
wpwrakwell, today it wasn't too bad. only about 3 hours from arrival to departure20:30
wpwrakand no surprise costs20:30
kristianpaulwpwrak: congrats !20:32
kristianpaulno adidional feeds either?20:32
kristianpaulwhitequark: to get started you dont need a fully capable board20:33
kristianpauljust and fpga you can program and a serial port20:33
whitequarkkristianpaul: well, I've relocated recently20:35
whitequarkI don't even have a soldering iron. almost nothing, actually20:35
whitequarknot even a single atmega :)20:35
whitequarkso I20:35
whitequark*I'm thinking what can I get the cheapest and quickiest way20:35
kristianpaulyou said you borrowed a nexsys2 dont you?20:37
whitequarknot yet20:45
whitequarkit's 00:45 here...20:45
whitequark15 minutes more, and there will be no working public transport20:46
whitequarkkristianpaul: okay. I've read several tutorials (including the NowWhat!?)23:07
whitequarkand assembled something that works in simulator23:07
whitequarkI think I'm starting to get the idea of how this stuff works.23:07
mwallelekernel: btw pep8 defines function names to be lower_case_with_underscores()23:39
whitequarksigh. python.23:40
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