#milkymist IRC log for Sunday, 2011-09-11

wpwrake.g., in labsw, i get what seems to be induction from the load to the wires going to the buttons00:00
larscbut it will just be a small bounce, or not?00:01
wpwrakin a sufficiently nasty scenario, these current changes could be periodic ...00:01
larsci still don't see how they could confuse the debouncer00:03
wpwrakso i'll err on the safe side and add a bit of extra filtering00:03
larscor do you mean that the signal will never be stable?00:03
wpwrakthe debouncer may see a seemingly stable signal for a while00:03
wpwrakat least in theory. it's kinda hard to test this in practice :)00:05
wpwraksuch things come and go. i already had to go through my whole set of lab power supplies to just make simple upsets happen occasionally. ironically, M1 is about 10x more effective at causing such things.00:06
qi-botThe build was successfull, see images here: http://fidelio.qi-hardware.com/~xiangfu/build-milkymist/milkymist-openwrt.minimal-09112011-0135/00:30
larschm, i suppose you could emulate edge triggered behaviour by switching between the trigger level, when the interrupt occurs00:32
larscbut you could miss a edge if your irq handler is to slow00:35
wpwrakyes, that should work00:44
larscsometimes it feels as if place and route is done by bruteforce02:37
kristianpauli mean surelly it is, but did you detected it some how?02:42
larscit takes ages ;)02:44
wpwraklarsc: what else would you expect in a proprietary and closed ecosystem where all selective pressure has been carefully eliminated ? ;-)06:23
lekernelwpwrak, nothing prevents you from writing a p&r tool07:50
wpwraklekernel: why duplicate your fine work ? :)10:22
larsclekernel: do you know any good articles/papers on p&r?11:57
lekernelthere's also this super-expensive book http://www.eecg.toronto.edu/~vaughn/book/arch_and_cad.html but it's just elaborating on the paper (I read it)12:00
lekernelthere's nothing groundbreaking in the book that you can't find out reading the paper and doing a little research12:01
lekernelif you still want to read it, it's available in some big libraries12:01
lekernelother than that one paper which isn't bad, in general you shouldn't expect much from academic research. if you want the beefy stuff, find papers and articles written by synopsys/cadence/altera/xilinx engineers12:05
lekernelUS patent 6301693 is very interesting too12:06
lekernelyou can also check out "Highly Efficient Gradient Computation for Density-Constrained Analytical Placement" from I¬¬¬ (you need to get past the paywall, ask me if it gives you trouble)12:07
lekernelbut I think that for starters, a "simple" simulated annealing like in VPR would be OK12:09
larsci can access ieee through my university vpn12:09
lekernelit seems Altera actually used an unpublished modified VPR to design the Stratix12:11
lekernelcheck out The Stratix Routing and Logic Architecture (David Lewis*, Vaughn Betz*, David Jefferson, Andy Lee, Chris Lane, Paul Leventis*, Sandy Marquardt*, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, and Jonathan Rose*)12:12
errordeveloperlekernel: have you had a look at that vrq thing ?13:24
lekernelyes, well, it's just a verilog parser13:44
lekerneldoesn't do any synthesis or p&r13:44
errordeveloperok, that's what I thought14:37
qi-botThe build was successfull, see images here: http://fidelio.qi-hardware.com/~xiangfu/build-milkymist/milkymist-openwrt.minimal-09112011-1811/17:06
mwallelekernel: im updating the uart core documentation atm. what does THRU mean?18:26
mwalleit enables loopback, but what does THRU stand for?18:26
rohmidi thru?18:28
rohmidi thru is usually a amplified copy of the 'in' port while 'out' is something 'generated' by a midi device18:28
rohmeans the in goes into the optocoupler and its output to a) a driver (logic gate or so) and the thru output and b) the input of the microcontroller (or whatever)18:30
rohthe out goes also to a driver and the 'out' port18:30
mwalleah midi terminology :)18:33
mwalleroh: thx :)18:36
rohyeah. midi is crude ;)18:40
GitHub120[linux-milkymist] mwalle force-pushed new-uart from 73ec00d to c1132a2: http://git.io/-D74Cw20:25
GitHub120[linux-milkymist/new-uart] lm32: update driver for new uart core - Michael Walle20:25
lekernelmwalle, "thru" connects TX to RX20:34
lekerneland yes, the term comes from MIDI20:34
lekernelare you planning to convert the other cores to level-sensitive as well?20:38
mwallelekernel: dunno, i want to look at the other linux drivers and make them devtree compatible20:50
lekernelwell, either use level-sensitive or edge-sensitive IRQs in the whole SoC, but not a mix :)20:50
mwalleac97? :b20:52
lekernelbtw, what is the advantage of having only one IRQ line from the UART to LM32? (as opposed to two like before)20:53
mwallewell not really any advantage nor any disadvantage imho, but one irq for uart devices fits better into the linux uart core driver :)20:54
mwalleeg. i dont need my own uart core descriptor object just for handling two interrupt numbers20:54
mwalleand i need the additional bits within the core anyway for polling20:55
lekernelwhat I don't like is it wastes IM bits and duplicates its functionality in the core, but if it makes writing drivers easier, it's acceptable20:56
lekernelthough it seems you want to use IM in the LM32 CPU-specific port and the "interrupt mask" core registers in the drivers already...20:58
mwallelekernel: right,20:59
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