#milkymist IRC log for Sunday, 2011-08-14

Fallenoulekernel: have you moved your debian repository for gtkterm and gcc-lm32 somewhere else ?13:48
Fallenoudeb http://www.milkymist.org/debian/ ./13:49
Fallenouthis does not work anymore13:49
lekernelit was old and unmaintainable, since i'm not using debian anymoe13:49
lekernelso I removed it13:49
lekernelall new software uses the rtems toolchain anyway13:50
Fallenouyep there is a tutorial about how to compile the toolchain on the wiki13:50
Fallenouand a few rpms I guess on rtems website13:51
kristianpaulthere is a script also for buils almost everyhting14:55
kristianpauls/for buils/to build14:55
Fallenouyep which is really usefull since there is much more dependencies now than at the beginning :)14:56
kristianpauldependencies, oh yeah....15:12
GitHub171[linux-milkymist] mwalle created new-uart (+1 new commit): http://bit.ly/pAcBqz17:53
GitHub171[linux-milkymist/new-uart] lm32: update driver for new uart core - Michael Walle17:53
kristianpaulmwalle: full rewrite?18:16
mwallekristianpaul: uart core?18:24
mwalleno only some small changes ;)18:25
mwallekristianpaul: btw did you get all 7 mails?18:25
mwallethat is 6 patches and one cover letter18:25
FallenouI got the seven mails18:26
mwalleah theres an archive, so i can verify it myself ;)18:26
kristianpaulyes all of then18:27
mwallekk so then we'll see us in two weeks :)18:27
kristianpauloh, bye then!18:28
mwalleat least regularly, maybe there will be some open wlan18:28
mwalleand maybe someone will find the bug, why some rx chars are dropped :)18:29
kristianpaulthose status and control bits should be mirrored/copied to others core  as well to make easy linux support?18:33
mwallei think some already have those18:33
mwalleas a rule of thumb, a linux driver should not need to touch the IP register of the processor18:35
kristianpaul(some alredy) hum, yes, now i was wonder why uart doesnt if was already part of CSR :)18:39
Fallenoumwalle: holidays ?18:40
mwalleFallenou: yeah :)18:40
Fallenouahah have fun :)18:40
kristianpaulwhere you going btw?18:40
kristianpaulnice, go to the beach is always refreshing, most if an island18:47
Fallenoulekernel: is configuring gcc with --disable-multilib wrong ?19:37
Fallenoumultilib thingies are still blurry to me19:39
FallenouAs I understood multilib is here to provide multiple libgcc with different configurations, but we only want/need one configuration19:40
Fallenouso I guess no need multilib19:41
lekernelif you only build the multilib with all the CPU options enabled (divider, barrel shifter, ...) that's fine, at least for milkymist19:48
lekernelmultilibs are a simple thing19:48
lekernelthey're only the same libraries built for CPUs with different options (with/without multiplier, divider, etc.)19:48
lekernelthe LM32 implementation has all the options enabled, but by default, the libraries built by GCC leave out some of them, which makes software slower19:49
GitHub8[milkymist] sbourdeauducq pushed 1 new commit to master: http://bit.ly/r6D3qd19:56
GitHub8[milkymist/master] gdbstub: cosmetic cleanups - Michael Walle19:56
lekernel<lekernel> if you only build the multilib with all the CPU options enabled (divider, barrel shifter, ...) that's fine, at least for milkymist20:04
lekernel multilibs are a simple thing20:04
lekernel they're only the same libraries built for CPUs with different options (with/without multiplier, divider, etc.)20:04
lekernel our LM32 implementation has all the options enabled, but by default, the libraries built by GCC leave out some of them, which makes software slower20:04
Fallenouok thanks for the explanation20:10
Fallenoulekernel: is there a way to check which cpu options are enabled ?20:12
FallenouI tried gcc -dumpspecs20:12
lekerneloption like -mdivide-enabled, -mmultiply-enabled are passed to gcc for that purpose20:12
Fallenouit outputs this :20:13
Fallenou%{mmultiply-enabled} %{mdivide-enabled} %{mbarrel-shift-enabled} %{msign-extend-enabled} %{muser-extend-enabled} %{v}20:13
Fallenoueven without your patch20:13
lekernela sure way to check is to disassemble the generated libraries and check for the optional instructions20:13
lekernelbut it'd tend to thing that, using the --without-multilib option, gcc would build libraries without any option20:14
Fallenouyes that's what I feared20:14
FallenouI removed the --without-multilib and am recompiling20:14
Fallenouhum it's compiling newlib right now20:15
Fallenougot lines like this :20:15
Fallenou/opt/local/var/macports/build/_Users_fallen_ports_cross_lm32-rtems-gcc/lm32-rtems-gcc/work/build/./gcc/xgcc -B/opt/local/var/macports/build/_Users_fallen_ports_cross_lm32-rtems-gcc/lm32-rtems-gcc/work/build/./gcc/ -nostdinc -B/opt/local/var/macports/build/_Users_fallen_ports_cross_lm32-rtems-gcc/lm32-rtems-gcc/work/build/lm32-rtems4.11/mbarrel-shift-enabled/msign-extend-enabled/newlib/ -isystem /opt/local/var/macports/build/_Users_fallen_ports_cross_lm320:15
Fallenousorry for the flood20:15
Fallenouit seems it's not putting all the optimizations20:15
Fallenouoh wait, looking at the directory path , it seems it's compiling a version with just those two cpu optimizations ...20:16
Fallenoumaybe it will compile another version with all the optimizations ...20:17
Fallenouthat's just crazy ...20:17
lekernelyeah it compiles for all the options20:18
Fallenouand all combinaisons ?20:18
lekernelit takes a bit of time, but cpu and disk space are cheap those days :-)20:18
Fallenoucrazy gcc is crazy20:18
lekernelit's not that big20:19
FallenouWill try to disable multilib and see if it does compile only one libc libm etc, but with the right options20:22
FallenouI hope so20:22
Fallenouan extract of the lm32-rtems4.11-gcc -dumpspecs : http://pastebin.com/DHr7XAh820:27
lekernelwell, as long as it works...20:29
Fallenoulekernel: I think if you put MULTILIB_OPTIONS = a/b/c/d instead of a b c d20:30
Fallenouif will only build the abcd combinaison20:30
Fallenouwill try20:30
mwallelekernel: what happens if you ack the interrupt right after entering the isr20:53
lekernelthe CPU can still miss a second event while it's doing things like setting stack frames, reading IP, etc.20:54
lekernelmh, no20:55
mwallemh? if i do sth like, irq fires, isr is called, ack irq, read stat, do stuff, return20:55
mwallethere could be additional isr calls which actually do nothing20:56
lekernelno, that would work20:58
mwalleso thats not the bug, because its done that way21:05
kristianpaulbtw, i always wondered how DataBusErros are handled by lm32 and by then by software running on it, for example a slave wishbone core that never reply an ACK21:09
lekernelkristianpaul, bus error jumps to exception, no ack reply locks up21:10
lekernelmwalle, let's not spend time debugging this, since this will be changed to level sensitive interrupts later21:11
lekernelwhich have no such problem21:11
mwallelekernel: using level sensitive interrupt and acking tx int by reading STAT and acking rx by reading STAT or reading RXTX ?21:18
lekerneldo not perform any action on CSR reads (just return values) - since the CSR bus has no strobe signal, it would react to invalid addresses on the bus21:19
lekernelfor interrupts, you can use bits that atomically clear when written with 1 in STAT21:21
lekerneloh, and maybe the STAT register should not have an interrupt enable feature... can't IM be used?21:22
lekerneleither implement interrupt enables in the core or IM, but not both21:23
mwallefor normal operation you wont need explicit interrupt acks imho, otho gdbstub needs something like that21:24
mwalleno i have to disable the interrupts without accessing IM21:24
lekernelso, should we remove IM?21:24
mwalleremember IM/IP/IE is only accessible from arch/lm32 code21:24
mwalleif we remove IM linux wont be able to mask spurious interrupts21:25
lekernelis that important?21:26
mwallei would say yes :)21:26
lekernelwhat do you mean, no explicit interrupt acks?21:26
lekernelyou should not alter the core state on a CSR read21:27
mwalleuart rx int fires, you read RXTX, int is automatically acked, no need to perform any w1c or anything like that21:27
lekernelwhen csr_we = 0, the addresses can correspond to either a valid read or anything21:28
kristianpaullekernel: (locks up) this is just a design missing feature from lm32 or something could be handled better therically implementated in the wishbone arbiter?21:28
lekernelthere's no strobe signal for reads21:29
mwalle(implicit acks) the 16550 does it that way21:29
lekernelyes, but i'd guess the 16550 has some form of read strobe signal21:30
mwalleassign rx_rd = csr_selected & !csr_we & (csr_a[2:0] == 3'b000);21:30
lekernelcsr_selected is not a strobe signal, it just means that four bits of the address have some value21:31
mwallemh ok, then this could be the bug :)21:32
lekernelif you use registers that modify state when read, it would react correctly when e.g. 0xe000d000 is read21:32
lekernelbut also induce a spurious state modification when 0x4000d000 (and others) are read by the CPU in SDRAM21:33
mwalleok, so DR should be w1c?21:37
lekernelcsr_selected & csr_we, otoh, is a valid write strobe signal21:39
mwalleyeah, and THRE wont need to be acked, a little bit asymmetrical21:40
lekernelyou can make THRE w1c as well, no?21:42
lekernelto ack the interrupt when there are no more characters to be transmitted21:43
mwallethen i would name it TD, or TX_DONE or sth like that, but i couldnt spin on it anymore21:45
mwallewhich is needed for a polling uart driver (gdbstub and linux console)21:46
lekernelso keep thre21:46
mwallestat = {tx_done, rx_event, thre} ?21:48
mwalletx_done and rx_event is w1c and irq = (tx_int_en & tx_done) | (rx_int_en & rx_event)21:49
lekernelsounds good21:49
lekerneland do you still need the interrupt masks then?21:49
mwalleyes i need to be able to disable irq without accessing IM21:49
mwallebtw (irq reordering) i didnt want to clutter the patch :)21:55
mwallegn8 and byebye22:11
mwallesee u22:11
Fallenousee u22:13
Fallenouenjoy your holydays22:13
mwallethx Fallenou22:13
--- Mon Aug 15 201100:00

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