#milkymist IRC log for Thursday, 2011-07-21

aw_rc3-0x2f: after 14.5 hrs rendering, then continue to test power-rendering (15 seconds) count; 60 times06:30
kristianpaulgood !06:36
kristianpaulevening aw_ :)06:37
aw_kristianpaul, evening :)06:37
aw_6506:38
aw_7006:44
aw_7506:51
aw_wpwrak_, how to transfer this to jpeg/png/pdf? http://downloads.qi-hardware.com/people/werner/m1/rc3/fix2-c238-variation-preview.ps06:56
aw_8006:57
aw_wpwrak_,  i'd like upload it to wiki if you don't mind. ;-)06:58
wpwrak_easy :)  ps2pdf file.ps file.pdf07:06
aw_how about convert to jpeg?07:07
wpwrak_(regarding the content) to my shame, i have to admit that i still haven't found a way to get it to calculate the lowest point in each sweep. all i get is the lowest point in all sweeps.07:07
wpwrak_hmm, better png07:07
aw_yeah..ok to png07:08
wpwrak_convert print.ps print.png07:08
wpwrak_well, s/print/file/g :)07:09
kristianpaulnow what adam need to apt-get install to make all this work? :-)07:09
aw_good, i converted done. tks07:11
wpwrak_for better quality, you can use: cat file.ps | gs -sDEVICE=ppmraw -sOutputFile=- -dTextAlphaBits=4 -dGraphicsAlphaBits=4 -q - | convert - file.png07:12
aw_hmm..but background is messy07:12
aw_OMG07:12
aw_try again07:12
wpwrak_kristianpaul: (install) yeah. fear the dependencies ;-)07:12
wpwrak_aw_: that's how the experts do it :)07:13
aw_8507:13
wpwrak_aw_: bonus points if you can type the command without looking at your cheat sheet ;-)07:13
aw_wpwrak_,  supposedly i am not defitely expert though. ;-)07:13
wpwrak_aw_: if you memorize this command, you can pass as one :)07:14
aw_9007:19
wpwrak_aw_: did the long command work ?07:23
aw_9507:26
wpwrak_aw_: and, and while you're at it, you may want to rotate and trim/crop: ... | convert -trim -rotate 90 - file.png07:26
aw_wpwrak_, try them after 100 , tks SIR. ;-O07:27
aw_10007:33
aw_wpwrak_, done that long command work, but right top corner equation is trimmed some. :(07:36
wolfspraulaw_: how are things going? any new problems?07:37
wpwrak_yeah, there are frequently problems with sheet sizes/bounding boxes. this will fix it:07:38
wpwrak_cat file.ps | | gs -sDEVICE=ppmraw -sOutputFile=- -dTextAlphaBits=4 -dGraphicsAlphaBits=4 -sPAPERSIZE=a4 -q - | convert -trim -rotate 90 - file.png07:38
aw_wpwrak_, http://downloads.qi-hardware.com/people/adam/m1/pic/m1_rc3_fix2-c238-variation-preview.png07:38
aw_alright, try again07:39
aw_wolfspraul, just get 100 times on rc3-0x2F power - rendering.07:44
aw_also 0x30 has gotten 1st 24 hours rendering at 15:30. ;-)07:45
wolfspraulok, all as it should be07:45
wolfspraulany news on when you get the 87 boards?07:45
aw_called today, they said might tonight or tomorrow morning to go through through hole reflow process.07:46
aw_as fast as i can get friday later or Saturday morning.07:47
aw_http://en.qi-hardware.com/wiki/File:M1_rc3_fix2-c238-variation-preview.png07:50
aw_wpwrak_, tks07:50
aw_http://en.qi-hardware.com/wiki/Milkymist_One_run_3_schedule#Hardware_Patches_of_Boot_up07:51
wolfspraulok understood, so maybe tomorrow :-)07:53
aw_maybe, so they will let me know tonight.07:53
wpwrak_aw_: great ! oh, and if you want it bigger, you can add the option -rDPI to the invocation of "gs". the default is -r72   bigger numbers increase the number of pixels07:55
aw_wpwrak_, used a r600 now, updated, tks.08:04
wpwrak_wow. r600 will be monstrous ;-)08:04
lekernelwpwrak_, lattice use synplify for synthesis, which has few bugs08:11
lekernelbut neocad-like tools for p&r, like xilinx08:11
wpwrak_lekernel: so you suspect the delays are there to cover up some problems in the verilog ?08:13
lekernelthey are here to cover up problems with simulation08:13
lekernelthe delays do nothing in synthesis08:14
lekernelone of the things that are very bad with verilog is that simulation results are non deterministic in some cases ...08:14
lekernelthat's an horrible time sink and an horrible source of bugs08:15
lekernel(in synchronous synthesis, one of those non-deterministic cases is picked up in a deterministic way, and then you get differences between simulation and implementation ...)08:16
wpwrak_hmm. and you can't make sure only one case remains ?08:16
lekernelyeah but then you lose useful language features08:16
wpwrak_sounds as if the problem would go away if synthesizer and simulator shared the same interpretation/preferences08:17
lekernelor you can use vhdl, which does not have this problem08:17
lekernelhttp://www.sigasi.com/content/verilogs-major-flaw08:18
wpwrak_seems ugly to have important language features to depend on non-determinism08:18
lekernelhttp://www.sigasi.com/content/vhdls-crown-jewel08:18
wpwrak_yes yes, you've posted that one at least twice already ;-)08:19
wpwrak_that too :)08:19
wpwrak_dunno. i find the approach of splitting things into "major" and "minor" phases a bit kludgy as well08:20
lekernelthose issues are also irrelevant for synchronous systems, like most FPGA designs...08:20
lekernelthey just create problems for free here08:20
wpwrak_why can't simulation be synchronous as well ?08:20
lekernelthere are some synchronous simulators, e.g. Verilator - but last time I checked, it had bugs08:21
wpwrak_ah well :)08:22
wpwrak_seems that the real problem is that simulator and synthesizer don't quite agree on what to do. apparently, even to the point where the simulation does not do what the verilog says, if i understand your complaint correctly ?08:23
lekernelhttp://issuu.com/xcelljournal/docs/xcell_journal_issue_76/54?viewMode=magazine&mode=embed09:48
lekernel....09:48
lekernelwpwrak_, yes, or you can get simple stupid behaviour in simulation09:48
Action: kristianpaul not going to learn VHDL anytime soon..10:47
wpwrak_lekernel: (archiving) oh dear. that world of closed source and no revision control must be so much fun ...12:16
wpwrak_lekernel: (stupid behaviour) i'm still a bit puzzled about that bit. so that would be something that does what the verilog says but it still not what - you think - the verilog means ?12:17
lekernellook at the sigasi links12:17
lekernelit could mean that something like this12:17
lekernelalways @(posedge clk) reg2 = reg1;12:18
lekernelalways @(posedge clk) reg3 = reg2;12:18
lekernelwould correspond to 0, 1 or 2 registers, depending on how the simulator orders the events ...12:18
lekernelwhile the designer obviously wants a shift register with 2 stages12:19
lekernelto remove the ambiguity, one could use the non blocking assignment "<=" instead of "="12:20
lekernelwhich is the right thing to do in this example12:20
wpwrak_great, problem solved :)12:20
lekernelbut there are more complex cases where the blocking assignment "=" is useful12:20
lekernele.g.12:20
lekernelreg = reg + 1;12:21
lekernelif(reg > 5) reg = 0;12:21
wpwrak_there, the ambiguity is resolved by the data dependency ?12:21
lekernelno, the problem is here that you have a register "reg" that uses blocking assignments and is probably read from a different "always" block12:22
lekernelthe code can be rewritten with the non blocking assignment as12:22
lekernelreg <= reg + 1;12:22
lekernelif(reg > 4) reg <= 0;12:22
lekernelbut if there was a more complex operaion than "+1", it quickly becomes messy12:23
wpwrak_so the reg = reg+1  and the  if (reg > 4) reg = 0  would be in different blocks ?12:24
lekernelsee this for example:12:24
lekernelhttps://github.com/milkymist/milkymist/blob/master/cores/tmu2/rtl/tmu2_geninterp18.v12:24
lekernelno, those two would be in the same always block. but typically you'll want to read "reg" from another place12:25
lekernelthe geninterp18 design is theoretically incorrect, since I rely on a particular ordering of events (which matches the deterministic one of synchronous design synthesis) - the code simply happens to work with the way gplcver orders the events...12:27
lekernela lot of designers use this kind of dirty workaround12:27
wpwrak_mmh, bad12:27
wpwrak_such things have their equivalent in the software world of course. you'd be surprised by how many programs break if you make "char" unsigned, even though ANSI C clearly states that "char" can be signed or unsigned. and then there are things like word sizes, etc.12:29
lekernelyeah, such things should not exist12:29
wpwrak_so yes, each language is surrounded by a "grey zone" of unspecified behaviour that people just expect to be in a certain way, but that isn't guaranteed. seems to be one of these cases.12:29
lekernelit's plainly bad language design12:29
wpwrak_i don't know. there are things you cannot find. especially not in concurrent designs.12:30
wpwrak_"you" = a compiler or such12:30
larscwpwrak_: not to count all those programs which would brake if you'd make char 7-bits ;)12:30
lekernelwpwrak_, vhdl solved this problem of verilog with the use of 'variables'12:31
lekernelwhich are like verilog's regs, but local to the equivalent of an always block12:32
lekernelso you do not have this nasty problem which arises when you have communication between always blocks with blocking assignments12:32
wpwrak_larsc: that should be even more fun :) well, there were the old CDC mainframes, with 6 bit characters :)12:35
wpwrak_so vhdl removed the problem of synchronizing access to global variables by removing global variables ?12:36
lekernelmaybe you should read the sigasi posts :) I can't really explain it better than that12:38
wpwrak_my so far purely theoretical understanding of these things doesn't go quite deep enough to grasp the finer points of what he wrote, but to me it seems that there are simply two paradigms that describe different things, where vhdl has a very rigid timing model and verilog is more similar to a traditional programming language that gives the compiler a lot of freedom to order things in the way it likes best12:42
lekernelit gives the _simulator_ some non-determinism, which does not have any purpose except wasting people's time12:43
wpwrak_based on this, i would expect vhdl to easily lead to designs that are either inefficient (because you spread them out over to many clock cycles) or cluttered (because you have to cram everything into one place to escape the rigid timing barriers), while verilog would suffer many of the usual misconceptions we know from C in concurrent designs12:44
lekernelno, there is no disadvantage to the vhdl variable12:45
wpwrak_it would still seem to me that the non-determinism is fundamental to the language semantics. one way to avoid it would be to tighten the language until there can no longer be any ambiguity, but that may lead to overly complex and inefficient designs (basically, micro-management)12:45
larscread the articles ;)12:46
lekernelnah... maybe you should read up a bit on how simulators, synchronous designs, and logic synthesis work :)12:46
wpwrak_the other path would be to break the simulation into two parts: the execution, and the validation of the concurrent behaviour12:46
wpwrak_larsc: reading he articles does't tell me how well the ideas work in practice :)12:47
wpwrak_(breaking the simulation into two parts) the execution would then share a set of conventions external to the language/definition proper that would make it generate the same behaviour as the synthesis12:48
wpwrak_while the validation would actively explore the ambiguities and ensure that all interpretations are valid12:49
wpwrak_that way, your simulation could be directly compared to real hardware (as in matching simulated and real scope traces)12:49
lekernelthere's an easier way to ensure same behaviour in simulation/synthesis: the vhdl delta delay algorithm and the use of the 'variable' container ....12:50
wpwrak_while your validation would tell you where you left ambiguities that conflict with your design (and it would allow you to keep ambiguities that don't)12:50
lekernelverilog should copy it... and remove those stupid reg/wire containers as well12:50
wpwrak_can't you just do the same by never using = on global variables in verilog ?12:50
wpwrak_well, in llhdl, there's your chance to clean up some things ;-)12:51
lekernelyes, but then you lose the functionality of the blocking assignment12:51
wpwrak_think of gcc. that one also has a lot of extensions. some of which later got incorporated into standard C12:51
lekernelllhdl is for synchronous synthesis, and synthesizers already do the right thing12:51
lekernelthe problem is only for general (not necessarily synchronous) simulation, and it also impacts simulation of synchronous systems12:52
wpwrak_(losing blocking assignments) you could still use it on non-global variables, no ?12:52
lekernelyes, but in turn some tools seem to have issues with mixing blocking and non-blocking assignments in the same always block...12:53
wolfspraulwi 4512:53
wolfspraulsorry12:53
wpwrak_so again, if your set of conventions to avoid ambiguities is to use synchronous synthesis (i have to admit that it's not intuitively clear to me what exactly this means, though), then perhaps all you really need is a simulator that follows the same conventions12:54
wpwrak_lekernel: (broken tools) well, but that's not a defect of the language :)12:54
wpwrak_actually, i wouldn't be surprised if the average verilog tool would be better quality than the average vhdl tool, simply because verilog looks less forbidding12:56
wpwrak_and maybe it's deceptive as well, in making things look friendly even if these things are inherently unfriendly12:57
wpwrak_btw, C also has its crutches. e.g., the linux kernel is written in a dialect of C with rather interesting extended semantics, which include things like memory barriers.12:58
wpwrak_memory barriers are something that doesn't exist in C. there's only the largely implementation-specified "volatile". but the language has no concept of, say, "shared memory"13:00
wpwrak_but that's where you can help a bit with dialects :)13:00
larscthe por13:01
wpwrak_the linux kernel language is at the same time also a subset of C, because there are many constructs gcc warns about (some of these warnings are very useful, others are of questionable value) and there are more constructs that are frowned upon by other human or automated reviewers13:02
larscthe problem with non blocking assignments is, that if you don't put them in synchronized blocks you've effectivly created an endless loop13:04
lekernelhm?13:07
larscor maybe not13:08
lekernelcan you give an example?13:08
larscyes, but the example leads to an endless loop with blocking assignments too, so...13:09
wpwrak_lekernel: btw, in your code, things like  o_r = o_r - 18'd1;  is the  18'd   because the synthesizer, when doing the calculation, doesn't see that the target is 18 bits wide ?13:11
lekerneli'm not sure if those prefixes are needed at all with modern tools ...13:12
wpwrak_good :)13:13
wpwrak_they look like maintenance nightmares. e.g., if you change the variable size and then have all those repetitions of the size scattered all over the code. a bit like excessive use of casts in C13:13
GitHub118[milkymist] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/milkymist/commit/5bfeabba3bce0776113b93750f753fcfd9677f3013:14
GitHub118[milkymist/master] TMU prefetch: texel fetch - Sebastien Bourdeauducq13:14
lekernelthere's myhdl which looks pretty nice13:14
wpwrak_yeah, indeed13:15
wpwrak_maybe there's a worthy contender13:15
wpwrak_by the way, if you want to brutally maximize concurrency, you should look at Promela. it's a very nice and light-weight language, a bit like C13:21
wpwrak_it's used for modeling concurrent behaviour (and then validating properties of it)13:21
wpwrak_one way to view it is that you put a number of assertions into your "program" and the validator will then execute some or all of the possible paths, and tell you what happened when it hits an assertion failure13:23
wpwrak_"what happened" includes the full execution history13:24
GitHub38[milkymist] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/milkymist/commit/156c0ca7b72bef6ef24beaf710648b7aa1a9154a13:33
GitHub38[milkymist/master] TMU prefetch: configurable memory data FIFO depth - Sebastien Bourdeauducq13:33
kristianpauli agree that closed-sourced tools may leed to unfair critism to hdl languages, ie verilog :)14:18
wpwrak_kristianpaul: indeed. and lekernel has it within his grasp to change the rules of the game. maybe have an option --good-sheep for llhdl, which makes it accept all the "standard" verilog he can stomach. if the option is omitted, extensions become available and constructs he dislikes produce nasty warnings. in each version, there can be more extension and warnings. a bit of constant prodding goes a long way ;-)15:00
GitHub91[milkymist] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/milkymist/commit/8c17500aa9a907817704ef8429d92519d7a4d4eb17:26
GitHub91[milkymist/master] TMU prefetch: top level design - Sebastien Bourdeauducq17:26
mwallelarsc: ?17:33
mwallelekernel: btw is it possible to support full speed devices?18:46
mwalleif there will be a real usb host controller someday18:46
lekernelyes, full speed devices should work22:57
larscmwalle: still there?22:57
lekernelin theory, simply by changing the navre firmware. in practice, you will probably uncover enough pesky bugs to keep you busy for several days ...23:00
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