#milkymist IRC log for Saturday, 2011-04-30

kristianpaulxiangfu: how long take your mm1 to load flicernoise?03:07
kristianpaulI'm not sure but with current resolution seems the jpg wallpaper add some delay for gui loading...03:08
xiangfu~13 secs03:09
xiangfuafter press three button for reboot03:09
xiangfukristianpaul: yes. depends on the wallpapers size.03:10
kristianpaulthis is with last bios commits? as seems milkymist splah logo was disable at boot03:10
kristianpaulhmm03:10
xiangfukristianpaul: no.03:11
kristianpaulk03:11
kristianpaulis it size of cpu usage at the when processing the jpg..?03:11
kristianpaulhumm03:11
kristianpaulignore 'at the'03:12
xiangfukristianpaul: the wallpaper have to be png03:12
xiangfukristianpaul: are you using a jpg wallpaper?03:13
kristianpaulah sorry, no no03:13
xiangfukristianpaul: I have test before if the png wallpaper size big. it needs more time to load.03:14
kristianpauli just using xiangfu's image ;-)03:14
xiangfukristianpaul: without any wallpaper it's faster.03:14
kristianpauli see :-)03:14
kristianpaulyeah, i just noticed that today03:15
xiangfuI also using xiangfu's image :)03:28
wolfspraulxiangfu: boot time is very important, I suggest for your next image by default you leave the wallpaper out then03:47
wolfspraulit should boot into rendering automatically anyway, imo03:48
xiangfuwolfspraul: ok03:56
azonenbergHave you guys considered DVI output at all?06:34
azonenbergThey added TMDS support in spartan-3a06:34
azonenbergi havent worked with the 6 but i assume it's there06:34
wolfspraulazonenberg: yes definitely lekernel thought about this, and it's doable afaik. One of the nearly infinite things that _could_ be done.07:56
wolfspraulhe is also thinking about s-video and tv-out support (with a vga to tv-out adapter cable)07:57
wolfspraulso far there is only lekernel doing such kind of work thought, so it's all up to his prioritizations and overview over the complete project as to when it's done07:57
wolfspraulunless someone like you comes along and lends a helping hand :-)07:57
lekernelwolfspraul: btw, if we start rearranging the power supply components, maybe it's a good time to start thinking about making room for a HDMI connector13:33
lekernel(I don't know where Adam is planning to put those zeners and fuse ...)13:34
kristianpaulvga to HDMI? :-)14:43
lekernelno, direct HDMI14:43
wolfspraullekernel: how big are those components? I didn't even ask Adam about size (or cost) yet, I just hope this is settled asap and we can move forward :-)15:19
lekernelit's just a HDMI connector and perhaps some ESD protection parts (0402 or the like)15:23
lekernelit goes straight to the fpga15:24
larscthis probably been discussed already, but why not displayport instead of HDMI?15:24
lekernelbut let's not delay rc3 for that, especially since it won't be supported in the fpga design anytime soon15:24
lekernelhdmi is used more often15:24
kristianpauli agree with larsc idea, actually wpwrak also pointed a interesting feature of adding a small lcd display to the box :-)15:25
larscmy new laptop has a dual-mode displayport connetor which allows connecting both displayport and HDMI cables.15:26
larscimo that would be the best option for the milkymist15:27
wolfspraullekernel: now I meant the size of the fuse and zeners15:27
wolfspraulI hope this is all small and won't cause layout issues15:28
lekernellarsc: isn't supporting those two standards a significant technical mess (USB-like)?16:08
larschm, actually i have no idea16:11
azonenberghdmi is more complex than dvi16:13
azonenbergin software16:13
azonenbergits a packet based protocol16:13
larschttp://en.wikipedia.org/wiki/DisplayPort#Compatibility_with_HDMI.2FDVI16:13
azonenberghavent actually implemented either but was reading up on them a while ago16:13
lekernelisn't HDMI just digital DVI with the possibility to fit additional packetized data (audio streams, DRM crap, ...) into the padding bytes?16:14
azonenberglekernel: First, iirc DVI supports HDCP as well16:18
azonenbergThough i've never considered implementing it for obvs reasons :P16:18
azonenbergBut yeah, both are TMDS at the physical layer16:18
azonenbergLayer 2 is either raw video data (DVI) or interleaved frames of video and other data (HDMI)16:19
azonenberglekernel: Lol, you and me are the only fans of sputter deposition on fb16:21
azonenbergSomething tells me it's not the most popular subject16:21
lekernelhmm... I thought there were HDMI->DVI passive adapter and the other way around16:24
lekernelmaybe HDMI displays can also accept raw video data16:24
azonenberglekernel: Thats possible16:26
azonenbergIt's also possible that the HDMI headers are in the blanking interval16:26
azonenbergSo that you can transparently feed them to DVI16:26
azonenbergBut going the other way around almost certainly involves adding packet headers16:26
azonenbergI'm not sure, like i said i havent actually implemented either yet16:27
azonenbergI do know they are compatible at the physical layer, both are R/G/B encoded as TMDS plus a clock at the pixel frequency (i.e. 1/10 the bit rate)16:28
lekernelanyone has experience with the elphel theora encoder?17:50
lekernelhttp://elphel.cvs.sourceforge.net/viewvc/elphel/camera333/fpga/x333/17:50
lekernellooks a bit messy17:50
lekernelhttp://elphel.cvs.sourceforge.net/viewvc/elphel/camera333/fpga/x333/x333.v?view=markup17:50
lekernel20% of the code or so is commented, same in other files17:51
lekernelhttp://elphel.cvs.sourceforge.net/viewvc/elphel/camera333/fpga/x333/reorder_hilbert.v?view=markup17:51
lekernelmclk0,    // system clock, phase 0 (@negedge) clk,      // this module clock (trying negedge - may change to reduce ground bounce17:51
lekernelwtf ...17:51
azonenberg?17:52
azonenbergis he suspecting ground bounce inside the fpga?17:52
azonenbergSounds like bad power filtering to me17:53
lekernelyeah, same here17:53
azonenbergnot enough vccint bypass caps etc17:53
azonenbergor enough but too big/too small/too fast/too slow17:53
lekerneland I can't see any reason for an hardware computation accelerator in FPGA to mess up with the clocks instead of being a pure synchronous design17:54
azonenbergYeah17:54
azonenbergi'm sure you know more about fpga stuff than i do (just getting started) but that much seems clear17:54
lekernelalso I don't see any test bench and I don't really believe that such code can be debugged by just downloading to FPGA ... maybe I'm looking in the wrong place17:59
lekernelweird18:00
lekernelthey have written a nice article http://www.elphel.cn/article/xc_video53.pdf but it doesn't say much either18:01
kristianpaulany updates related to coming Fedora 15?23:08
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