| terpstra | lekernel, (option b! option b!) | 08:11 |
|---|---|---|
| larsc | mwalle: more or less | 09:33 |
| juliusb | lekernel: hejsan, how are you? | 09:41 |
| juliusb | I recall you had a synthesis tool you were working on, how is that going? | 09:42 |
| juliusb | and where can I find the site it was on - I couldn't find a link from the milkymist website | 09:42 |
| lekernel | hi | 09:44 |
| lekernel | it's moving forward, though a bit slowly, my main priority is milkymist | 09:44 |
| lekernel | lately I was analyzing the s6 bitstream format a bit | 09:44 |
| juliusb | cool | 09:45 |
| juliusb | yes I recently got a spartan6 board | 09:45 |
| juliusb | still fixing issues on my older Xilinx boards but hope to get it working soon | 09:45 |
| juliusb | ... but where is the synthesis project's source? I've seen it before but forgot what it was called | 09:45 |
| lekernel | code is here=> github.com/sbourdeauducq | 09:45 |
| lekernel | there's also a little doc at https://github.com/sbourdeauducq/llhdl/wiki | 09:46 |
| juliusb | cool, thanks | 09:47 |
| lekernel | which s6 board did you get? m1? :p | 09:47 |
| juliusb | digilent atlys | 09:52 |
| juliusb | i haven't even started synthesizing for it to be honest | 09:52 |
| juliusb | interested to see the advance in technology | 09:52 |
| lekernel | why not M1? | 09:57 |
| juliusb | what is M1? | 10:00 |
| juliusb | that Xilinx one? | 10:01 |
| lekernel | our board... http://www.milkymist.org/mmone.html | 10:01 |
| juliusb | we got the atlys quite cheap | 10:01 |
| juliusb | it looks good, yours actually | 10:01 |
| juliusb | how much is it? | 10:01 |
| juliusb | how much to get one to my door? | 10:01 |
| juliusb | running off for lunch, be back later | 10:02 |
| lekernel | 380E + shipping | 10:02 |
| guyzmo | ola | 10:06 |
| guyzmo | lekernel - I did get some basic lua stuff to work, but nothing fancy | 10:07 |
| guyzmo | it would be nice if I could be able to output something (video, sound, dmx...) from the MM1 with lua code | 10:08 |
| guyzmo | to show off something better than just a lua interpreter blackbox | 10:09 |
| lekernel | imo dmx is easier | 10:09 |
| lekernel | http://keplerproject.github.com/luafilesystem/manual.html | 10:10 |
| lekernel | complement **the set of functions related to file systems offered by the standard Lua distribution**. | 10:10 |
| lekernel | imo you already have everything you need for DMX in that standard distribution | 10:10 |
| guyzmo | lekernel - and do you have a rtfm to write well formatted DMX datagrams into the matching chardev ? | 10:13 |
| lekernel | you don't have to format the DMX frames, the hardware does it for you | 10:13 |
| lekernel | all you need to do is: | 10:13 |
| lekernel | 1) open /dev/dmx_out | 10:13 |
| lekernel | 2) seek to the channel you want (first position = channel 1, etc. by default the /dev file is opened at channel 1) | 10:14 |
| lekernel | 3) write one byte to set the level of that channel - if you write more than one byte it will also assign to the next channels | 10:14 |
| lekernel | 4) close /dev/dmx_out | 10:14 |
| guyzmo | interesting implementation | 10:15 |
| guyzmo | it sends the packet on flush() ? | 10:15 |
| lekernel | no, it sends the packet all the time with the memorized channel values | 10:15 |
| guyzmo | ok | 10:15 |
| lekernel | it's like a DMX desk, and using /dev/dmx_out you touch the faders :-) | 10:16 |
| guyzmo | ok, I'll get two DMX projectors for thursday and tomorrow I'll write a demo in lua | 10:18 |
| guyzmo | (I don't have a DMX projector at the bear's cave) | 10:18 |
| carlobar | lekernel: hi, i have made some changes on the hpdmc controller: on initialization i configure burst_length = 2, and now i made 32 bit read/write operations using burst, so i think that im ensuring a data flow during the burst length, but it still dont work. I dont know what else can i do, i dont know what is missing. any advice? thanks | 17:15 |
| lekernel | based on this scarce information, i'd advise you to buy a M1 which i've spent a year or so to get the SDRAM to work on | 17:18 |
| lekernel | have you run verilog simulations first, though? | 17:20 |
| carlobar | hahaha, yes, in simulation it read and write without problem | 17:20 |
| lekernel | including through the l2 cache? | 17:21 |
| carlobar | what is the l2 cache? simulation includes: csrbrg, fmlbrg, hpdmc, ddr... buffers, double date rate flip flops and the dcm_sp are simulated too. the problem that i had with IDDR2 and ODDR2 was solved adding a flip flop to each one, with that the behavior of these devices was achieved | 17:29 |
| carlobar | on spartan3, ODDR2 and IDDR2 can only be implemented with the parameter: DDR_ALIGNMENT = "NONE", so adding a flip flop, the behavior of DDR_ALIGNMENT = "C0" is achieved | 17:35 |
| lekernel | l2 cache is fmlbrg | 17:38 |
| carlobar | i remember that i had changed the fmlbrg, i had modified it to support fml with 32bit data bus, and i wasnt sure if it worked or not, so i changed it. the fmlbrg uses a state machine to control when an instruction is sent to the fml bus, and when a result is sent to the wishbone bus... | 17:51 |
| carlobar | these are the results when i write/read data: | 18:05 |
| carlobar | mr 0x40000000 16:: 0x40000000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | 18:05 |
| carlobar | mr 0x40002000 16:: 0x40002000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | 18:05 |
| carlobar | mw 0x40000000 0xfade2bad | 18:05 |
| carlobar | mr 0x40000000 16:: 0x40000000 fa de 2b ad 00 00 00 00 00 00 00 00 00 00 00 00 ..+............. | 18:05 |
| carlobar | mr 0x40002000 16:: 0x40002000 fa de 2b ad 00 00 00 00 00 00 00 00 00 00 00 00 ..+............. | 18:05 |
| carlobar | mw 0x40002000 0xabcdef00 | 18:05 |
| carlobar | mr 0x40002000 16:: 0x40002000 ab cd ef 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | 18:05 |
| carlobar | mr 0x40000000 16:: 0x40000000 ab cd ef 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ | 18:05 |
| carlobar | i thought that the memory didnt recognize the bank or row address, so i made tests changing the bank address, and write/read operations worked... | 18:11 |
| carlobar | im runing the system at a freq of 40MHz, so i modified the timing register | 18:15 |
| lekernel | did you disable the dll in the dram chip? | 18:24 |
| carlobar | you mean the "operating mode" at mode register? | 18:29 |
| lekernel | something like that | 18:30 |
| carlobar | it is in normal operation: 00000..... on the initialization sequence i just modified the burst length | 18:32 |
| carlobar | and added the instructions to change the timing register | 18:33 |
| carlobar | lekernel: do you spent one year working only on SDRAM or you were working in all the system? | 19:26 |
| lekernel | only on SDRAM. but those were in the ML401 days, and I didn't have as much insight into digital design as I have now. | 19:27 |
| lekernel | the M1 just uses roughly the same memory as the ML401 so I did not have to redesign that part | 19:28 |
| carlobar | i just realized that the problem is in directions: 0x40000000, 0x40002000, 0x40004000 and so on.., but sometimes when i read at that directions, previous data is replaced with 0x00000000 | 19:36 |
| mwalle | gdb patch is upstream and will be included in gdb 7.3 | 20:42 |
| lekernel | the break problem? great :) | 20:57 |
| mwalle | yep | 21:00 |
| mwalle | and there will be target dependent linking for qemu, eg link only to libGL if target==lm32, so it will be enabled by default again | 21:01 |
| lekernel | http://www.teralab.co.uk/X-Ray_Gallery/X-Ray_Gallery_Page1.htm | 21:39 |
| lekernel | made with http://www.teralab.co.uk/X-Ray_Gallery/X-Ray_Gallery_Page2.htm ...hahaha | 21:40 |
| wpwrak | lekernel: boring. should be with an electronic sensor. you could increase the resolution by vibrating the object. | 22:35 |
| --- Wed Apr 27 2011 | 00:00 | |
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