#milkymist IRC log for Tuesday, 2011-04-26

terpstralekernel, (option b! option b!)08:11
larscmwalle: more or less09:33
juliusblekernel: hejsan, how are you?09:41
juliusbI recall you had a synthesis tool you were working on, how is that going?09:42
juliusband where can I find the site it was on - I couldn't find a link from the milkymist website09:42
lekernelit's moving forward, though a bit slowly, my main priority is milkymist09:44
lekernellately I was analyzing the s6 bitstream format a bit09:44
juliusbyes I recently got a spartan6 board09:45
juliusbstill fixing issues on my older Xilinx boards but hope to get it working soon09:45
juliusb... but where is the synthesis project's source? I've seen it before but forgot what it was called09:45
lekernelcode is here=> github.com/sbourdeauducq09:45
lekernelthere's also a little doc at https://github.com/sbourdeauducq/llhdl/wiki09:46
juliusbcool, thanks09:47
lekernelwhich s6 board did you get? m1? :p09:47
juliusbdigilent atlys09:52
juliusbi haven't even started synthesizing for it to be honest09:52
juliusbinterested to see the advance in technology09:52
lekernelwhy not M1?09:57
juliusbwhat is M1?10:00
juliusbthat Xilinx one?10:01
lekernelour board... http://www.milkymist.org/mmone.html10:01
juliusbwe got the atlys quite cheap10:01
juliusbit looks good, yours actually10:01
juliusbhow much is it?10:01
juliusbhow much to get one to my door?10:01
juliusbrunning off for lunch, be back later10:02
lekernel380E + shipping10:02
guyzmolekernel - I did get some basic lua stuff to work, but nothing fancy10:07
guyzmoit would be nice if I could be able to output something (video, sound, dmx...) from the MM1 with lua code10:08
guyzmoto show off something better than just a lua interpreter blackbox10:09
lekernelimo dmx is easier10:09
lekernelcomplement **the set of functions related to file systems offered by the standard Lua distribution**.10:10
lekernelimo you already have everything you need for DMX in that standard distribution10:10
guyzmolekernel - and do you have a rtfm to write well formatted DMX datagrams into the matching chardev ?10:13
lekernelyou don't have to format the DMX frames, the hardware does it for you10:13
lekernelall you need to do is:10:13
lekernel1) open /dev/dmx_out10:13
lekernel2) seek to the channel you want (first position = channel 1, etc. by default the /dev file is opened at channel 1)10:14
lekernel3) write one byte to set the level of that channel - if you write more than one byte it will also assign to the next channels10:14
lekernel4) close /dev/dmx_out10:14
guyzmointeresting implementation10:15
guyzmoit sends the packet on flush() ?10:15
lekernelno, it sends the packet all the time with the memorized channel values10:15
lekernelit's like a DMX desk, and using /dev/dmx_out you touch the faders :-)10:16
guyzmook, I'll get two DMX projectors for thursday and tomorrow I'll write a demo in lua10:18
guyzmo(I don't have a DMX projector at the bear's cave)10:18
carlobarlekernel: hi, i have made some changes on the hpdmc controller: on initialization i configure burst_length = 2, and now i made 32 bit read/write operations using burst, so i think that im ensuring a data flow during the burst length, but it still dont work. I dont know what else can i do, i dont know what is missing. any advice? thanks17:15
lekernelbased on this scarce information, i'd advise you to buy a M1 which i've spent a year or so to get the SDRAM to work on17:18
lekernelhave you run verilog simulations first, though?17:20
carlobarhahaha, yes, in simulation it read and write without problem17:20
lekernelincluding through the l2 cache?17:21
carlobarwhat is the l2 cache? simulation includes: csrbrg, fmlbrg, hpdmc, ddr... buffers, double date rate flip flops  and the dcm_sp are simulated too. the problem that i had with IDDR2 and ODDR2 was solved adding a flip flop to each one, with that the behavior of these devices was achieved17:29
carlobaron spartan3, ODDR2 and IDDR2 can only be implemented with the parameter: DDR_ALIGNMENT = "NONE", so adding a flip flop, the behavior of DDR_ALIGNMENT = "C0" is achieved17:35
lekernell2 cache is fmlbrg17:38
carlobari remember that i had changed the fmlbrg, i had modified it to support fml with 32bit data bus, and i wasnt sure if it worked or not, so i changed it. the fmlbrg uses a state machine to control when an instruction is sent to the fml bus, and when a result is sent to the wishbone bus...17:51
carlobarthese are the results when i write/read data:18:05
carlobar mr 0x40000000 16:: 0x40000000  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................18:05
carlobar mr 0x40002000 16:: 0x40002000  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................18:05
carlobar mw 0x40000000 0xfade2bad18:05
carlobar mr 0x40000000 16:: 0x40000000  fa de 2b ad 00 00 00 00 00 00 00 00 00 00 00 00  ..+.............18:05
carlobar mr 0x40002000 16:: 0x40002000  fa de 2b ad 00 00 00 00 00 00 00 00 00 00 00 00  ..+.............18:05
carlobar mw 0x40002000 0xabcdef0018:05
carlobar mr 0x40002000 16:: 0x40002000  ab cd ef 00 00 00 00 00 00 00 00 00 00 00 00 00  ................18:05
carlobar mr 0x40000000 16:: 0x40000000  ab cd ef 00 00 00 00 00 00 00 00 00 00 00 00 00  ................18:05
carlobari thought that the memory didnt recognize the bank or row address, so i made tests changing the bank address, and write/read operations worked...18:11
carlobarim runing the system at a freq of 40MHz, so i modified the timing register18:15
lekerneldid you disable the dll in the dram chip?18:24
carlobaryou mean the "operating mode" at mode register?18:29
lekernelsomething like that18:30
carlobarit is in normal operation: 00000..... on the initialization sequence i just modified the burst length18:32
carlobarand added the instructions to change the timing register18:33
carlobarlekernel: do you spent one year working only on SDRAM or you were working in all the system?19:26
lekernelonly on SDRAM. but those were in the ML401 days, and I didn't have as much insight into digital design as I have now.19:27
lekernelthe M1 just uses roughly the same memory as the ML401 so I did not have to redesign that part19:28
carlobari just realized that the problem is in directions: 0x40000000, 0x40002000, 0x40004000 and so on.., but sometimes when i read at that directions, previous data is replaced with 0x0000000019:36
mwallegdb patch is upstream and will be included in gdb 7.320:42
lekernelthe break problem? great :)20:57
mwalleand there will be target dependent linking for qemu, eg link only to libGL if target==lm32, so it will be enabled by default again21:01
lekernelmade with http://www.teralab.co.uk/X-Ray_Gallery/X-Ray_Gallery_Page2.htm ...hahaha21:40
wpwraklekernel: boring. should be with an electronic sensor. you could increase the resolution by vibrating the object.22:35
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