| carlobar | hi, i have modified the the HPDMC controller in order to support 16 bits memories, but i got errors and i dont know whats wrong. | 00:09 |
|---|---|---|
| carlobar | The HPDMC write/read 16 bit data, so i made an entity that perform 2 read/write to get a 32 bit data. | 00:09 |
| carlobar | I can read/write data using the bootloader, but when i try to write at 0x40002000, the data at 0x40000000 is overwriten, and i dont understand why. I made a simulation of a write operaion at 0x40002000, but it looks fine, someone can help me? | 00:09 |
| kristianpaul | hmm, icap allows multiboot | 02:34 |
| kristianpaul | but is not clear to me if xilinx support partial reconfigurarion or core load/unload.. in spartan6.. | 02:34 |
| kristianpaul | all what i found is about virtex | 02:34 |
| kristianpaul | multiboot still nice, but not the main goal.. | 02:35 |
| kristianpaul | well, if you can resume and reboot fast enought... ;) | 02:42 |
| kristianpaul | he,, http://www.xilinx.com/itp/xilinx7/books/data/docs/dev/dev0036_8.html | 02:46 |
| kristianpaul | where is my xilinx7 :D ??!! | 02:47 |
| kristianpaul | "current implementation of the bus macro uses eight 3-state buffer" ohh, 3 state | 02:51 |
| kristianpaul | and saying, okay i can do reconfigure partially, it will be not much that two "modules" it seems.. | 03:02 |
| kristianpaul | bah, i forgot check ack before read wb_data_i .. | 03:47 |
| lekernel | carlobar: see fml doc, you need an uninterrupted stream of data, which means your hack cannot work unless you also double the DDR frequency | 10:19 |
| lekernel | (you can also just buy a M1 *g*) | 10:20 |
| lekernel | kristianpaul: partial reconfiguration works for spartan6, but as always it's bloody and dirty | 10:32 |
| lekernel | it doesn't use 3 state buffers though (the s6 doesn't have them anyway) | 10:32 |
| lekernel | and you can have as many modules as you want (or, more exactly, 1/16 of the FPGA tile count on S6, but that's a lot :p) but you have to be prepared to hack the tools and/or the bitstream files quite heavily for that, depending on how much flexibility you need | 10:35 |
| kristianpaul | lekernel: (partial reconfiguration in s6) how do you know that? already tried? got some paper about it? or.. | 10:41 |
| lekernel | i'm using the partial reconfiguration features to reverse engineer the bitstream format more easily | 10:41 |
| kristianpaul | :o | 10:42 |
| kristianpaul | ha, cheating, you are taking apart the bistream using partial reconf! | 10:42 |
| kristianpaul | make sense | 10:43 |
| lekernel | jeje | 10:48 |
| kristianpaul | (it doesn't use 3 state buffers though) so, what it uses? | 10:49 |
| kristianpaul | a special secret xilinx unviversal bus? :p | 10:49 |
| lekernel | http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/ug702.pdf | 10:54 |
| lekernel | this is more up to date | 10:54 |
| lekernel | but for s6 they don't support it (and they said they will never) but many things should work anyway | 10:55 |
| kristianpaul | ah | 10:56 |
| lekernel | http://forums.xilinx.com/t5/Spartan-Family-FPGAs/partial-dynamic-reconfiguration-for-Spartan-6/td-p/62517 | 10:56 |
| lekernel | they have this "difference based" reconfiguration too | 10:56 |
| lekernel | (which is officially supported for s6) | 10:56 |
| lekernel | guyzmo: hi | 16:05 |
| lekernel | did you get some lua stuff to work? | 16:06 |
| kristianpaul | not in a mipsel machine.. | 16:17 |
| kristianpaul | oops | 16:17 |
| kristianpaul | :D | 16:35 |
| Action: lekernel wonders about the other features of that bot | 16:35 | |
| kristianpaul | lol | 16:40 |
| kristianpaul | at least joking is on the list of features | 16:41 |
| kristianpaul | s/joking/humor | 16:41 |
| lekernel | !joke | 16:41 |
| lekernel | !fortune | 16:41 |
| scrts | lol :) | 19:12 |
| mwalle | larsc: are you an openwrt developer? | 21:50 |
| trem | nite all, sweet dreams | 21:57 |
| --- Tue Apr 26 2011 | 00:00 | |
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