| kristianpaul | Fallenou: yeah, i'm havin lots of power problems this weak :( | 01:36 |
|---|---|---|
| kristianpaul | damit | 01:36 |
| kristianpaul | Fallenou: is up now | 01:40 |
| kristianpaul | arggh, powr failure. data storage failure... :/ | 01:40 |
| xiangfu | kristianpaul: I upload the makefile to a new repo : http://projects.qi-hardware.com/index.php/p/m1s/source/tree/master/ | 02:14 |
| xiangfu | kristianpaul: fyi :) | 02:14 |
| kristianpaul | good | 02:15 |
| kristianpaul | I'll have more time to try out on before friday | 02:16 |
| kristianpaul | ok, now where is the dma arbiter... | 04:30 |
| lekernel | http://www.sigasi.com/content/your-milage-may-vary-lot | 10:53 |
| kristianpaul | "You may not (and may not allow anyone else to) disclose the results of any benchmarking of a Licensed Product (whether or not the results were obtained with assistance from [the EDA vendor]) to any third party" patetic | 11:15 |
| kristianpaul | lekernel: can i say dma is mm soc is an implementation of a wishbone swich topology, and of course the cpu is the master 1? | 14:01 |
| kristianpaul | morning btw :-) | 14:01 |
| lekernel | it's a multi-master wishbone with (partial) crossbar switch | 14:01 |
| Fallenou | lekernel: is fml crossbar switch or pipeline or shared bus ? | 14:33 |
| Fallenou | topology | 14:33 |
| lekernel | hmm | 14:33 |
| lekernel | what would be the point of a crossbar? | 14:33 |
| Fallenou | I don't even understand the crossbar | 14:34 |
| Fallenou | it's just to know which one it is | 14:34 |
| lekernel | well, then read up on crossbars first, then ask yourself how many slave peripherals there are on FML and this should answer your question | 14:34 |
| Fallenou | I thought I could have a quicker answer here, obviously a mistake | 14:35 |
| lekernel | crossbars allow simultaneous communication between different masters each talking to a different slave | 14:36 |
| Fallenou | ok | 14:37 |
| lekernel | here there's only one slave, the sdram controller | 14:38 |
| lekernel | so it's obviously a shared bus | 14:38 |
| Fallenou | ok thanks | 14:38 |
| terpstra | is lm32 support in mainline gcc now? | 15:23 |
| Fallenou | it's been in mainline gcc for some time now | 15:32 |
| Fallenou | it's not recent | 15:32 |
| lekernel | it was thrown into gcc 4.5 without much advertisement | 15:33 |
| terpstra | great | 15:34 |
| lekernel | maybe I should update the gcc website myself :) | 15:34 |
| Fallenou | it's been two years ? something like that ? | 15:34 |
| lekernel | i'm just a bit afraid of using CVS and breaking things... | 15:34 |
| lekernel | one year | 15:34 |
| Fallenou | ok | 15:34 |
| lekernel | we also have serious issues with the C++ compiler - it seems to generate broken code in 4.5.x and no longer builds in 4.6 | 15:36 |
| Fallenou | even the gcc-core-4.5.2 from rtems.org with their patch ? | 15:39 |
| Fallenou | it's generating kroken code ? | 15:39 |
| Fallenou | broken* | 15:40 |
| lekernel | yes | 15:40 |
| lekernel | at least it seems so | 15:40 |
| terpstra | lekernel, the g++ i have from lattice works | 15:41 |
| lekernel | I ran into the Qt4 broken method table bug with that one, and Till also had broken code issues | 15:41 |
| terpstra | though i've not built large programs with it | 15:42 |
| lekernel | but it's 3.x, no? | 15:42 |
| lekernel | or a modified 4.4 | 15:42 |
| terpstra | its 4.3.0 | 15:42 |
| lekernel | yeah ok :) | 15:42 |
| lekernel | gcc seems to be such a mess to maintain, they regularly break stuff... :( | 15:42 |
| lekernel | especially "minor" architectures | 15:43 |
| Fallenou | I guess they don't even test those minor architectures | 15:46 |
| Fallenou | do they even have testsuites for those ? | 15:46 |
| lekernel | http://udrepper.livejournal.com/7326.html | 15:47 |
| Fallenou | lol | 15:48 |
| lekernel | iirc someone spoke about a gcc build farm on the ML... somewhere around July 2009 | 15:48 |
| lekernel | I should contact him back to add some lm32 tests, even basic (just check that the compiler builds) to his suite | 15:49 |
| Fallenou | Examples for this are plenty. Many of the GNU projects are ported to a wide variety of platforms, even to undeserving once like cygwin and mingw | 15:50 |
| Action: Fallenou lol'ed | 15:50 | |
| lekernel | yeah, sometimes by rms himself :) | 15:51 |
| Fallenou | ahah so funny to read http://sources.redhat.com/ml/libc-announce/2001/msg00000.html | 16:04 |
| lekernel | yeah, I read that too some time ago... | 16:08 |
| lekernel | free software isn't exactly the ideal world some advocacy organizations depict :) | 16:09 |
| Fallenou | yeah it seems so | 16:09 |
| Fallenou | lol Xilinx was routing power to blockram even if the blockram block was un used | 17:36 |
| Fallenou | they started to stop powering unused blockram in the 7 serie | 17:36 |
| Fallenou | 30% of the power leakage was coming from unused blockram :) | 17:37 |
| Fallenou | let's turn off the light please if you don't use it ! | 17:37 |
| lekernel | hmm??? | 17:44 |
| lekernel | from what I can tell, leakage power in current FPGAs isn't that big anyway, so there can be a justification for that :) | 17:45 |
| lekernel | also, 28nm would leak more | 17:45 |
| Fallenou | well they are saying 28 nm is leaking less | 17:45 |
| Fallenou | Learn about the power benefits of the 28nm process Xilinx 7 Series #FPGA in this NEW white paper. http://bit.ly/WP28nm <= | 17:46 |
| lekernel | probably B.S. | 17:46 |
| Fallenou | lol | 17:46 |
| Fallenou | anyway, funny that they just happen to think about not powering what's not used by the design | 17:46 |
| lekernel | what it could mean is the leakage power per transistor is lower, but *all* the power per transistor is lower in 28nm, including dynamic power | 17:46 |
| lekernel | but the leakage/dynamic power ratio grows as process geometries shrink | 17:46 |
| lekernel | if they reduced it, it's not by switching to 28nm | 17:47 |
| lekernel | this actually makes things worse | 17:47 |
| Fallenou | humm ok | 17:47 |
| lekernel | btw, it'd be fun to get kintex7 support in llhdl before they generally sell the devices =] | 17:51 |
| lekernel | the reverse engineering process should be largely automated, and k7 isn't very different from s6 | 17:53 |
| lekernel | so once s6 works great, supporting k7 should be a walk in the park | 17:53 |
| Fallenou | 18:44 < lekernel> btw, it'd be fun to get kintex7 support in llhdl before they generally sell the devices =] | 18:02 |
| Fallenou | LOL | 18:02 |
| kristianpaul | hehe | 18:03 |
| Fallenou | they could be very happy about that | 18:04 |
| Fallenou | I hope they will | 18:04 |
| Fallenou | or they could wake up a bunch of lawyers :) | 18:04 |
| kristianpaul | at least us will be happy :-) | 18:04 |
| kristianpaul | or they can offer a big fat job to lekernel ;-) | 18:05 |
| kristianpaul | ergg, ignore fat | 18:05 |
| kristianpaul | lekernel: are curently automating reverse eng process for s6? | 18:06 |
| Fallenou | his code parse Xilinx big fat information files about s6 arch | 18:07 |
| kristianpaul | I was thinking in ulogic actually | 18:09 |
| scrts | heh :) | 18:28 |
| scrts | I have a friend that is able to crack any altera megacore | 18:28 |
| scrts | which is encrypted | 18:29 |
| scrts | maybe someone did that for xilinx cores? | 18:29 |
| Fallenou | scrts: ask lekernel he told me about some xilinx core decryption one day | 19:03 |
| Fallenou | the key was somewhere distributed with the ise | 19:03 |
| scrts | well, for altera cores decryption the core ID is needed only | 19:04 |
| scrts | like 4 symbols code | 19:04 |
| Fallenou | lol | 19:04 |
| Fallenou | and then you get the all hdl source code ? | 19:04 |
| kristianpaul | netlist he get i think | 19:05 |
| scrts | yes | 19:05 |
| scrts | the source is available with quartus | 19:05 |
| scrts | it is only encoded | 19:05 |
| scrts | run the decoder and get the verilog files | 19:05 |
| scrts | move them to the altera ip core dir | 19:05 |
| scrts | regenerate the core | 19:05 |
| scrts | and no time limits :) | 19:06 |
| Fallenou | hehe :) | 19:07 |
| Fallenou | I never used encrypted core before | 19:08 |
| Fallenou | they have time limit ? | 19:08 |
| scrts | yep, works ~1hour in silicon | 19:08 |
| Fallenou | o_o | 19:08 |
| Fallenou | must be a big register to hold that much time information | 19:08 |
| scrts | hmm, I am not sure | 19:08 |
| kristianpaul | you can make a clock div and count cycles | 19:08 |
| scrts | afaik it is counted @ pc, because when You disconnect the jtag the core stops | 19:09 |
| Fallenou | well how do you know the clock freq ? | 19:09 |
| Fallenou | oh | 19:09 |
| Fallenou | ok | 19:09 |
| Fallenou | it sucks :( | 19:09 |
| Fallenou | is it the same with Xilinx closed-source IP ? | 19:09 |
| scrts | dunno | 19:09 |
| scrts | I use xilinx at home and altera at work | 19:10 |
| scrts | never used closed source xilinx cores | 19:10 |
| Fallenou | Has your friend written a blog post about that ? | 19:10 |
| Action: kristianpaul used to work with nios | 19:10 | |
| scrts | the cores needed @ work were SDI based | 19:10 |
| Fallenou | SDI ? | 19:10 |
| scrts | serial digital interface | 19:11 |
| scrts | video standard :) | 19:11 |
| Fallenou | oh ok | 19:11 |
| scrts | mostly used in professional studies | 19:11 |
| Fallenou | didn't know this interface | 19:11 |
| lekernel_ | scrts: I can also crack Xilinx encrypted IP, but there is nothing really interesting in there | 22:55 |
| lekernel_ | and it's not even hard to crack | 22:55 |
| lekernel_ | it's also illegal to use them... which makes it even less interesting | 22:57 |
| Fallenou | lekernel_: do you have the source of your slides of 26C3 ? | 22:58 |
| lekernel_ | mom, I'm not sure... maybe lost them in a hdd failure last year | 22:58 |
| Fallenou | I am rewritting some pages since I don't have the source code | 22:58 |
| Fallenou | would help me :) | 22:58 |
| Fallenou | ooh too bad | 22:58 |
| Fallenou | otherwise I can continue rewritting | 22:58 |
| lekernel_ | I have the sources of the university conference last month though | 22:59 |
| lekernel_ | http://lekernel.net/presentations/masteri2l/ | 22:59 |
| lekernel_ | (but in french) | 22:59 |
| Fallenou | oh | 22:59 |
| Fallenou | I was not aware of this one | 22:59 |
| lekernel_ | ah, I also have http://lekernel.net/presentations/Milkymist_BEC/ | 23:00 |
| lekernel_ | with the source | 23:00 |
| Fallenou | sure | 23:00 |
| Fallenou | I based my slides on this | 23:00 |
| Fallenou | and backported some other informations from the RMLL2010 talk | 23:00 |
| lekernel_ | but I can't find any trace of the 26c3 sources... | 23:00 |
| Fallenou | and used the design from RMLL2010 (prefer the yellow) | 23:00 |
| Fallenou | I just want to add some technical informations from 26C3 | 23:01 |
| Fallenou | ok no problem | 23:01 |
| Fallenou | will just rewrite what I need | 23:01 |
| lekernel_ | kristianpaul: the s6 reverse engineering automation is being done by the ulogic authors | 23:02 |
| lekernel_ | who are on mm and llhdl lists btw | 23:02 |
| lekernel_ | and yeah for the chip geometry we can parse the xdlrc database | 23:05 |
| lekernel_ | also automatically | 23:05 |
| lekernel_ | the last difficult thing will be the timing model | 23:05 |
| Fallenou | nice presentation, the masteri2l | 23:11 |
| Fallenou | something weird | 23:12 |
| Fallenou | you say you have 3.2 Gb/s of max bandwidth , from your ddr sdram chip | 23:12 |
| Fallenou | and you say you need 3.3 Gb/s memory bandwidth | 23:13 |
| Fallenou | how is this possibly working ? | 23:13 |
| Fallenou | ok the cache | 23:13 |
| Fallenou | it's the only thing I can see that could help | 23:14 |
| Fallenou | if you access several times the same data | 23:14 |
| Fallenou | it can save you sdram bandwidth | 23:14 |
| Fallenou | lekernel_: how much sdram bandwidth are you using atm ? | 23:15 |
| lekernel_ | btw, HPDMC is scheduled to launch into space in January 2012 | 23:15 |
| Fallenou | :) | 23:15 |
| Fallenou | the end of the world :p | 23:16 |
| Fallenou | I knew it ! | 23:16 |
| lekernel_ | some 3-4 Gbps I think | 23:16 |
| lekernel_ | haven't measured with the video input and everything | 23:16 |
| lekernel_ | but the soc has a core to do that... there's a memory statistics command in the demo firmware but it's not in the rtems shell yet | 23:16 |
| Fallenou | ok so the sdram chip is capable of more than 3.2 Gb/s then ? | 23:16 |
| lekernel_ | each sdram chip has ~3.2Gbps peak bandwidth, and there are two | 23:17 |
| Fallenou | oh :) | 23:17 |
| Fallenou | which makes ~6.4 Gb/s peak ? | 23:17 |
| lekernel_ | yes | 23:18 |
| Fallenou | ok | 23:18 |
| lekernel_ | at least when running at 100MHz, when it's 80MHz it's a bit less | 23:19 |
| Fallenou | sure | 23:19 |
| lekernel_ | also, the DRAM control algorithm cannot reach the peak bandwidth in practice | 23:19 |
| Fallenou | because of column changing ? | 23:19 |
| lekernel_ | if I have time and motivation, i'll redo the complete SoC design at some point, with out-of-order memory transactions, prefetching and QoS | 23:20 |
| lekernel_ | it'd potentially multiply the memory bandwidth available in reality by a factor of 4 | 23:20 |
| Fallenou | wo :) | 23:20 |
| lekernel_ | (and then we could probably process HD video) | 23:21 |
| Fallenou | lekernel_: it is 16 bits sdram chips on the M1 ? | 23:30 |
| lekernel_ | yes | 23:31 |
| Fallenou | so it's a 32 bits data bus, with 16 bits from each chip ? | 23:31 |
| Fallenou | you sample at both rising and falling edge and you have 2 32 bits words per cycle ? | 23:31 |
| lekernel_ | yes | 23:33 |
| Fallenou | ok | 23:33 |
| Fallenou | when you say you do 4 reads bursts | 23:34 |
| Fallenou | each read is 32 bits ? | 23:34 |
| Fallenou | or 64 bits ? | 23:34 |
| mwalle | hi | 23:35 |
| mwalle | btw the avr core is a busmaster right? | 23:36 |
| Fallenou | hi | 23:36 |
| mwalle | we should route the 'break' signal to the avr core and write our own gdb stub :) | 23:36 |
| mwalle | disable uart in main lm32 | 23:37 |
| mwalle | and use it from within the avr core | 23:37 |
| mwalle | and we dont need any jtag2gdb bridge | 23:37 |
| mwalle | would be a cool gsoc project :) | 23:38 |
| lekernel_ | ah yes, definitely | 23:38 |
| lekernel_ | do you want to mentor that? :) | 23:39 |
| mwalle | maybe ;) | 23:39 |
| lekernel_ | Fallenou: each read is 64 bits | 23:39 |
| lekernel_ | mwalle: well, the deadline is tomorrow | 23:39 |
| mwalle | narf :) | 23:39 |
| mwalle | ill do it | 23:40 |
| lekernel_ | btw the avr core isn't a wishbone bus master, but it can send text messages to the lm32 which can forward them to the uart | 23:40 |
| mwalle | mh | 23:40 |
| lekernel_ | there's actually a debug print() function in the avr firmware that does exactly that | 23:41 |
| mwalle | ah i remember, theres a dual ported ram in between | 23:41 |
| lekernel_ | yes | 23:41 |
| mwalle | sorry i'm to tired, going to bed now | 23:42 |
| lekernel | feel free to edit http://www.milkymist.org/wiki/index.php?title=GSoC_application_2011 if you want to participate | 23:43 |
| mwalle | when exactly is the deadline tomorrow? | 23:43 |
| Fallenou | it's the deadline for mentoring organization | 23:44 |
| lekernel | March 11: 23:00 UTC | 23:44 |
| Fallenou | it's the 11 march 23 | 23:44 |
| lekernel | but we'll need to update the application in the google system before that | 23:44 |
| Fallenou | for this dead line you have to list the mentors ? | 23:44 |
| lekernel | yes | 23:44 |
| Fallenou | oh crap :( | 23:44 |
| Fallenou | the project list can be updated later on | 23:45 |
| Fallenou | but you need the mentor list | 23:45 |
| Fallenou | humm i'm not sure lekernel | 23:51 |
| Fallenou | http://www.google-melange.com/document/show/gsoc_program/google/gsoc2011/userguide#depth_orgapp | 23:51 |
| Fallenou | "Guide for Mentors" | 23:51 |
| Fallenou | Once an organization has had its application accepted, anyone who has created a site wide profile can apply to that organization as a mentor | 23:52 |
| lekernel | well they do ask for an initial mentor list | 23:52 |
| Fallenou | oh ok | 23:52 |
| lekernel | and probably attribute slots based on that | 23:52 |
| lekernel | actually, they ask tons of stuff and writing an application is a pain | 23:52 |
| lekernel | especially when they reject it with an automatically generated message | 23:52 |
| Fallenou | slots are attributed after student proposals | 23:52 |
| lekernel | and accept shitty projects like beagleboard instead | 23:52 |
| Fallenou | so I guess they take into account the total number of mentors | 23:52 |
| Fallenou | yes it's not perfect | 23:54 |
| Fallenou | but it's still a good thing, if it can provide debugguer or mmu :) | 23:54 |
| Fallenou | how many mentors do you have lekernel ? | 23:54 |
| Fallenou | I guess there is mwalle + you , and then who else ? | 23:56 |
| lekernel | maybe Eric Rannaud (one of the ulogic guys actually ;) and Jon | 23:58 |
| --- Thu Mar 10 2011 | 00:00 | |
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