#milkymist IRC log for Wednesday, 2011-03-09

kristianpaulFallenou: yeah, i'm havin lots of  power problems this weak :(01:36
kristianpaulFallenou: is up now01:40
kristianpaularggh, powr failure. data storage failure... :/01:40
xiangfukristianpaul: I upload the makefile to a new repo : http://projects.qi-hardware.com/index.php/p/m1s/source/tree/master/02:14
xiangfukristianpaul: fyi :)02:14
kristianpaulI'll have more time to try out on before friday02:16
kristianpaulok, now where is the dma arbiter...04:30
kristianpaul"You may not (and may not allow anyone else to) disclose the results of any benchmarking of a Licensed Product (whether or not the results were obtained with assistance from [the EDA vendor]) to any third party" patetic11:15
kristianpaullekernel: can i say dma is mm soc is an implementation of a wishbone swich topology, and of course the cpu is the master 1?14:01
kristianpaulmorning btw :-)14:01
lekernelit's a multi-master wishbone with (partial) crossbar switch14:01
Fallenoulekernel: is fml crossbar switch or pipeline or shared bus ?14:33
lekernelwhat would be the point of a crossbar?14:33
FallenouI don't even understand the crossbar14:34
Fallenouit's just to know which one it is14:34
lekernelwell, then read up on crossbars first, then ask yourself how many slave peripherals there are on FML and this should answer your question14:34
FallenouI thought I could have a quicker answer here, obviously a mistake14:35
lekernelcrossbars allow simultaneous communication between different masters each talking to a different slave14:36
lekernelhere there's only one slave, the sdram controller14:38
lekernelso it's obviously a shared bus14:38
Fallenouok thanks14:38
terpstrais lm32 support in mainline gcc now?15:23
Fallenouit's been in mainline gcc for some time now15:32
Fallenouit's not recent15:32
lekernelit was thrown into gcc 4.5 without much advertisement15:33
lekernelmaybe I should update the gcc website myself :)15:34
Fallenouit's been two years ? something like that ?15:34
lekerneli'm just a bit afraid of using CVS and breaking things...15:34
lekernelone year15:34
lekernelwe also have serious issues with the C++ compiler - it seems to generate broken code in 4.5.x and no longer builds in 4.615:36
Fallenoueven the gcc-core-4.5.2 from rtems.org with their patch ?15:39
Fallenouit's generating kroken code ?15:39
lekernelat least it seems so15:40
terpstralekernel, the g++ i have from lattice works15:41
lekernelI ran into the Qt4 broken method table bug with that one, and Till also had broken code issues15:41
terpstrathough i've not built large programs with it15:42
lekernelbut it's 3.x, no?15:42
lekernelor a modified 4.415:42
terpstraits 4.3.015:42
lekernelyeah ok :)15:42
lekernelgcc seems to be such a mess to maintain, they regularly break stuff... :(15:42
lekernelespecially "minor" architectures15:43
FallenouI guess they don't even test those minor architectures15:46
Fallenoudo they even have testsuites for those ?15:46
lekerneliirc someone spoke about a gcc build farm on the ML... somewhere around July 200915:48
lekernelI should contact him back to add some lm32 tests, even basic (just check that the compiler builds) to his suite15:49
FallenouExamples for this are plenty. Many of the GNU projects are ported to a wide variety of platforms, even to undeserving once like cygwin and mingw15:50
Action: Fallenou lol'ed15:50
lekernelyeah, sometimes by rms himself :)15:51
Fallenouahah so funny to read http://sources.redhat.com/ml/libc-announce/2001/msg00000.html16:04
lekernelyeah, I read that too some time ago...16:08
lekernelfree software isn't exactly the ideal world some advocacy organizations depict :)16:09
Fallenouyeah it seems so16:09
Fallenoulol Xilinx was routing power to blockram even if the blockram block was un used17:36
Fallenouthey started to stop powering unused blockram in the 7 serie17:36
Fallenou30% of the power leakage was coming from unused blockram :)17:37
Fallenoulet's turn off the light please if you don't use it !17:37
lekernelfrom what I can tell, leakage power in current FPGAs isn't that big anyway, so there can be a justification for that :)17:45
lekernelalso, 28nm would leak more17:45
Fallenouwell they are saying 28 nm is leaking less17:45
FallenouLearn about the power benefits of the 28nm process Xilinx 7 Series #FPGA in this NEW white paper. http://bit.ly/WP28nm <=17:46
lekernelprobably B.S.17:46
Fallenouanyway, funny that they just happen to think about not powering what's not used by the design17:46
lekernelwhat it could mean is the leakage power per transistor is lower, but *all* the power per transistor is lower in 28nm, including dynamic power17:46
lekernelbut the leakage/dynamic power ratio grows as process geometries shrink17:46
lekernelif they reduced it, it's not by switching to 28nm17:47
lekernelthis actually makes things worse17:47
Fallenouhumm ok17:47
lekernelbtw, it'd be fun to get kintex7 support in llhdl before they generally sell the devices =]17:51
lekernelthe reverse engineering process should be largely automated, and k7 isn't very different from s617:53
lekernelso once s6 works great, supporting k7 should be a walk in the park17:53
Fallenou18:44 < lekernel> btw, it'd be fun to get kintex7 support in llhdl  before they generally sell the devices =]18:02
Fallenouthey could be very happy about that18:04
FallenouI hope they will18:04
Fallenouor they could wake up a bunch of lawyers :)18:04
kristianpaulat least us will be happy :-)18:04
kristianpaulor they can offer a big fat job to lekernel ;-)18:05
kristianpaulergg, ignore fat18:05
kristianpaullekernel: are curently automating reverse eng process for s6?18:06
Fallenouhis code parse Xilinx big fat information files about s6 arch18:07
kristianpaulI was thinking in ulogic actually18:09
scrtsheh :)18:28
scrtsI have a friend that is able to crack any altera megacore18:28
scrtswhich is encrypted18:29
scrtsmaybe someone did that for xilinx cores?18:29
Fallenouscrts: ask lekernel he told me about some xilinx core decryption one day19:03
Fallenouthe key was somewhere distributed with the ise19:03
scrtswell, for altera cores decryption the core ID is needed only19:04
scrtslike 4 symbols code19:04
Fallenouand then you get the all hdl source code ?19:04
kristianpaulnetlist he get i think19:05
scrtsthe source is available with quartus19:05
scrtsit is only encoded19:05
scrtsrun the decoder and get the verilog files19:05
scrtsmove them to the altera ip core dir19:05
scrtsregenerate the core19:05
scrtsand no time limits :)19:06
Fallenouhehe :)19:07
FallenouI never used encrypted core before19:08
Fallenouthey have time limit ?19:08
scrtsyep, works ~1hour in silicon19:08
Fallenoumust be a big register to hold that much time information19:08
scrtshmm, I am not sure19:08
kristianpaulyou can make a clock div and count cycles19:08
scrtsafaik it is counted @ pc, because when You disconnect the jtag the core stops19:09
Fallenouwell how do you know the clock freq ?19:09
Fallenouit sucks :(19:09
Fallenouis it the same with Xilinx closed-source IP ?19:09
scrtsI use xilinx at home and altera at work19:10
scrtsnever used closed source xilinx cores19:10
FallenouHas your friend written a blog post about that ?19:10
Action: kristianpaul used to work with nios19:10
scrtsthe cores needed @ work were SDI based19:10
FallenouSDI ?19:10
scrtsserial digital interface19:11
scrtsvideo standard :)19:11
Fallenouoh ok19:11
scrtsmostly used in professional studies19:11
Fallenoudidn't know this interface19:11
lekernel_scrts: I can also crack Xilinx encrypted IP, but there is nothing really interesting in there22:55
lekernel_and it's not even hard to crack22:55
lekernel_it's also illegal to use them... which makes it even less interesting22:57
Fallenoulekernel_: do you have the source of your slides of 26C3 ?22:58
lekernel_mom, I'm not sure... maybe lost them in a hdd failure last year22:58
FallenouI am rewritting some pages since I don't have the source code22:58
Fallenouwould help me :)22:58
Fallenouooh too bad22:58
Fallenouotherwise I can continue rewritting22:58
lekernel_I have the sources of the university conference last month though22:59
lekernel_(but in french)22:59
FallenouI was not aware of this one22:59
lekernel_ah, I also have http://lekernel.net/presentations/Milkymist_BEC/23:00
lekernel_with the source23:00
FallenouI based my slides on this23:00
Fallenouand backported some other informations from the RMLL2010 talk23:00
lekernel_but I can't find any trace of the 26c3 sources...23:00
Fallenouand used the design from RMLL2010 (prefer the yellow)23:00
FallenouI just want to add some technical informations from 26C323:01
Fallenouok no problem23:01
Fallenouwill just rewrite what I need23:01
lekernel_kristianpaul: the s6 reverse engineering automation is being done by the ulogic authors23:02
lekernel_who are on mm and llhdl lists btw23:02
lekernel_and yeah for the chip geometry we can parse the xdlrc database23:05
lekernel_also automatically23:05
lekernel_the last difficult thing will be the timing model23:05
Fallenounice presentation, the masteri2l23:11
Fallenousomething weird23:12
Fallenouyou say you have 3.2 Gb/s of max bandwidth , from your ddr sdram chip23:12
Fallenouand you say you need 3.3 Gb/s memory bandwidth23:13
Fallenouhow is this possibly working ?23:13
Fallenouok the cache23:13
Fallenouit's the only thing I can see that could help23:14
Fallenouif you access several times the same data23:14
Fallenouit can save you sdram bandwidth23:14
Fallenoulekernel_: how much sdram bandwidth are you using atm ?23:15
lekernel_btw, HPDMC is scheduled to launch into space in January 201223:15
Fallenouthe end of the world :p23:16
FallenouI knew it !23:16
lekernel_some 3-4 Gbps I think23:16
lekernel_haven't measured with the video input and everything23:16
lekernel_but the soc has a core to do that... there's a memory statistics command in the demo firmware but it's not in the rtems shell yet23:16
Fallenouok so the sdram chip is capable of more than 3.2 Gb/s then ?23:16
lekernel_each sdram chip has ~3.2Gbps peak bandwidth, and there are two23:17
Fallenouoh :)23:17
Fallenouwhich makes ~6.4 Gb/s peak ?23:17
lekernel_at least when running at 100MHz, when it's 80MHz it's a bit less23:19
lekernel_also, the DRAM control algorithm cannot reach the peak bandwidth in practice23:19
Fallenoubecause of column changing ?23:19
lekernel_if I have time and motivation, i'll redo the complete SoC design at some point, with out-of-order memory transactions, prefetching and QoS23:20
lekernel_it'd potentially multiply the memory bandwidth available in reality by a factor of 423:20
Fallenouwo :)23:20
lekernel_(and then we could probably process HD video)23:21
Fallenoulekernel_: it is 16 bits sdram chips on the M1 ?23:30
Fallenouso it's a 32 bits data bus, with 16 bits from each chip ?23:31
Fallenouyou sample at both rising and falling edge and you have 2 32 bits words per cycle ?23:31
Fallenouwhen you say you do 4 reads bursts23:34
Fallenoueach read is 32 bits ?23:34
Fallenouor 64 bits ?23:34
mwallebtw the avr core is a busmaster right?23:36
mwallewe should route the 'break' signal to the avr core and write our own gdb stub :)23:36
mwalledisable uart in main lm3223:37
mwalleand use it from within the avr core23:37
mwalleand we dont need any jtag2gdb bridge23:37
mwallewould be a cool gsoc project :)23:38
lekernel_ah yes, definitely23:38
lekernel_do you want to mentor that? :)23:39
mwallemaybe ;)23:39
lekernel_Fallenou: each read is 64 bits23:39
lekernel_mwalle: well, the deadline is tomorrow23:39
mwallenarf :)23:39
mwalleill do it23:40
lekernel_btw the avr core isn't a wishbone bus master, but it can send text messages to the lm32 which can forward them to the uart23:40
lekernel_there's actually a debug print() function in the avr firmware that does exactly that23:41
mwalleah i remember, theres a dual ported ram in between23:41
mwallesorry i'm to tired, going to bed now23:42
lekernelfeel free to edit http://www.milkymist.org/wiki/index.php?title=GSoC_application_2011 if you want to participate23:43
mwallewhen exactly is the deadline tomorrow?23:43
Fallenouit's the deadline for mentoring organization23:44
lekernelMarch 11: 23:00 UTC23:44
Fallenouit's the 11 march 2323:44
lekernelbut we'll need to update the application in the google system before that23:44
Fallenoufor this dead line you have to list the mentors ?23:44
Fallenouoh crap :(23:44
Fallenouthe project list can be updated later on23:45
Fallenoubut you need the mentor list23:45
Fallenouhumm i'm not sure lekernel23:51
Fallenou"Guide for Mentors"23:51
FallenouOnce an organization has had its application accepted, anyone who has created a site wide profile can apply to that organization as a mentor23:52
lekernelwell they do ask for an initial mentor list23:52
Fallenouoh ok23:52
lekerneland probably attribute slots based on that23:52
lekernelactually, they ask tons of stuff and writing an application is a pain23:52
lekernelespecially when they reject it with an automatically generated message23:52
Fallenouslots are attributed after student proposals23:52
lekerneland accept shitty projects like beagleboard instead23:52
Fallenouso I guess they take into account the total number of mentors23:52
Fallenouyes it's not perfect23:54
Fallenoubut it's still a good thing, if it can provide debugguer or mmu :)23:54
Fallenouhow many mentors do you have lekernel ?23:54
FallenouI guess there is mwalle + you , and then who else ?23:56
lekernelmaybe Eric Rannaud (one of the ulogic guys actually ;) and Jon23:58
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