#milkymist IRC log for Sunday, 2011-03-06

mw1terpstra: do you write your own tool to use the lm32 jtag port with gdb? (that would be cool, even cooler if it was gpl :) )13:27
scrtsbtw, how much time does it take to synthesize/p&r/etc milkymist? :)13:28
kristianpaul35 minutes or so in my one core machine13:29
kristianpaullekernel: (pastebin) first routing it seems, nice !!, does it worK? or you got a short cicuit else where? ;-)13:31
lekernelcan't test on fpga yet... but the result looks coherent13:31
kristianpaulxiangfu: hi14:15
kristianpaulxiangfu: You should join #rtems as well, and i dont know if already rtems mail lists?14:15
kristianpaul(can't test on fpga yet) because missing part for a xilinx-like compliance bitstream generation?14:17
lekernelI could feed that back into the xilinx toolchain using xdl, but the problem is I don't handle I/O yet14:56
lekernelso no observable thing would happen14:57
wolfspraullekernel: just fyi, it seems China uses mostly PAL15:15
lekernelok, good15:17
lekernelbut taiwan is ntsc iirc15:17
lekernelFallenou: the rxbuff's should go to the softc too15:36
lekernelhttp://pastebin.com/VkpJbC08 what's that?15:38
wolfspraullekernel: sorry if this is a crazy question, but is it theoretically possible to process 3 different composite video signals over the 3 video-in jacks we have?15:43
lekernelno at the same time, but by switching them maybe15:43
wolfspraulthis needs to be supported/driven by the video codec chip?15:44
wolfspraulvideo decoder I mean...15:45
wolfspraulthe ad pdf says "includes a 6-channel input mux that enables multiple video signals..."15:47
wolfspraulok anyway, I think I got it. maybe it's possible, but it's experimental and there may be limitations.15:48
kristianpaulhaha, just i realize now we have 3 vide in jacks, i was thinking the other two were for audio..16:05
aerislekernel tu veux toujours que le firmware soit mono-fichier ?19:18
aerisPas d'image à coté ?19:18
lekernelquel firmware?19:21
lekerneltant que c'est pas le fouillis... il y a un système yaffs2 de toutes façons19:21
lekernelc'est pour quoi?19:21
aerisDes icones, entre autre19:22
mwallea further source for chip interna?22:31
lekernelbtw the current antares router simply dumps the complete interconnect graph from the tools, which makes it rather memory hungry but means I don't have to understand all of this (and irregularities e.g. I/O, DSP blocks, etc.)22:34
lekernelthe complete representation for the xc6slx4 uses about 70M22:35
lekerneloh, and I tried routing several signals with antares and fpga editor, both give exactly the same PIP lists now :)22:37
mwallenice :)22:39
CIA-31qemu-lm32: michael master * rf543d138 /target-lm32/ (lm32-decode.h translate.c): lm32: use lookup table for opcodes http://tinyurl.com/62n3aau22:42
CIA-31qemu-lm32: michael master * rc9fb6df5 /target-lm32/translate.c: lm32: rename raise opcode to scall http://tinyurl.com/6d6n55q22:42
lekernelmwalle: btw, do you happen to know if each value of the bitstream's frame address register (FAR) represents one tile in the FPGA?22:43
mwallelol, no :)22:46
lekernelknowing the FAR<=>tile mapping should make it rather easy to figure out the bitstream format22:47
lekernelmaybe I can get this information by playing with the partial reconfiguration features in ISE22:48
kristianpaulfrom #osmocom http://cgi.ebay.com/Ferrite-Core-Memory-Military-USSR-Soviet-Computer-/380320686712?pt=LH_DefaultDomain_0&hash=item588ce12278#ht_1810wt_113522:53
lekernelkristianpaul: might be fun to read it back :)22:58
lekernelthough there's probably lot of stuff in it... and maybe even not ASCII22:59
lekernels/lot/not a lot/22:59
lekernelI guess there are cheaper ones too...23:00
kristianpaulWhy ac97 core have a dma irq for r/w ?23:00
lekernellike with any irq: to avoid polling23:01
kristianpaulyeah, but in mean in system.v ac97dmar_irq23:03
Action: kristianpaul read more before ask again23:04
kristianpaulI mean ac97 also have ac97crreply_irq and  ac97crrequest_irq wires23:05
kristianpaulSo i noticed this for me *extra* wires labeled asac97dmar_irq and ac97dmaw_irq23:06
kristianpaulI should guess is something specific for the ac97 driver internals and i should read the datasheet also :-)23:06
Fallenou16:32 < lekernel> http://pastebin.com/VkpJbC08 what's that? < well it's the equivalent of the code that was there before, but it's in the softc now, I had a global array with registers addresses, in order to loop over it, now the array is in the softc, I initialize the array at registering time of the driver23:13
lekernelah, ok23:13
lekernelfor the rx buffers, I guess you can safely assume that malloc() returns an address aligned to a 32 bit boundary23:14
lekernelotherwise posix_memalign() is like malloc() but lets you specify the alignment23:14
Fallenouoh ok23:14
Fallenoufinally I did allocation with "static"23:15
Fallenouis it OK ?23:15
lekernelit's like a global variable.. better put that in the softc23:15
lekernelor use global variables everywhere, that works too23:15
kristianpaullekernel: FML is transparently accesed from wishbone thanks to the fml bridge, right?23:15
lekernelbut just avoid a misleading softc/global variable mix23:15
lekernelkristianpaul: yes23:16
Fallenoulekernel: when you say "put that in the softc" you mean sc->rxbuffers[i] = malloc(); ?23:16
Fallenoubecause it's in the softc now in the last version23:16
Fallenouwell the static declaration is not in the softc23:17
Fallenoubut the pointer is in it23:17
Fallenouand it's used through the softc23:17
kristianpaulso, the video-in, vga-out and tmu are already maped in fml also?23:17
kristianpaulFallenou: what is softc?23:17
Fallenoukristianpaul: the structure that holds all the driver-related pointers/data23:18
kristianpaulFallenou: oh, nice to know :-)23:19
Fallenoustruct minimac_softc in network.c23:19
lekernelkristianpaul: the only thing which is mapped in FML is the SDRAM. the other devices connected to it are masters (accessors)23:34
--- Mon Mar 7 201100:00

Generated by irclog2html.py 2.9.2 by Marius Gedminas - find it at mg.pov.lt!