#milkymist IRC log for Monday, 2011-02-28

wpwrakkristianpaul: (tuner on lpt) UBB ?!?04:58
wpwrak(age of tuner circuit) the html files are from 2007. also the PDF of the schematics says january 2007. amazing, all this looks more 1970-ish ;-)04:59
rohi dont get whats new there05:02
rohisnt it a dead boring default cable tuner?05:02
wpwrakdunno. maybe it has an unusually wide range or such ?05:06
rohnot that i can see05:23
wpwrakah well. maybe just good marketing then ;-)05:33
terpstrahello all!09:55
terpstraI've ported the LM32 from milkymist to a small SoC system for use on our Altera FPGAs. In the process I got the JTAG working and wrote a little tool that talks to the FPGA over the USB Blaster's JTAG. I've been able to happily load and execute small programs via this tool into the SRAM. As my next step I wanted to try to get gdb working (as a pre-step to configuring a kernel for our SoC). I've seen that milkymist somehow uses gdb with the LM32 alr09:58
terpstraeady. Where can I find out more about this?09:58
FallenouHi terpstra really nice job :)10:45
Fallenouis your project open source ? do you have a web page or something ?10:45
FallenouI would like to have a look :)10:45
terpstrait is open source10:46
terpstrabut it's not got a project page per-se10:46
terpstraat the moment i've been tasked to evaluate the alternative soft CPUs, and part of that is determining what they can do---jtag, simulation, debugger, toolchain, LUT size, speed, etc10:47
terpstrathe contenders are: leon3, openrisc1000, zpu, and lm3210:47
terpstraso if we end up picking the lm32, then it would end up as a visible part of the project10:48
terpstrai'd be happy to send you a tarball tho10:48
terpstraFallenou, am i mistaken about milkymist and gdb? all i've found is the page about using gdb with qemu, but i'm trying to get it to talk directly to the CPU in-chip10:49
FallenouI really don't know, sorry10:49
Fallenoubut mwalle or lekernel would know10:50
terpstrai already have a working connection to the CPU via JTAG and was just thinking of whipping up a small debug ROM on the instruction bus and a register dump WOM on the data bus10:50
terpstrabut i don't want to reinvent the wheel10:50
terpstraespecially the wheel that implements the gdbserver protocol10:50
FallenouYou can send an e-mail to the Milkymist mailing list if you want, it would be great to say a little "hello I am doing this and this about lm32" :)10:50
Fallenouit's always good to know what others are doing10:50
kristianpaulwpwrak: (UBB) yes, well, i need the 3V3 to 5V shifter, but is on my todo once i tune and can listen something..10:50
terpstraok, i'll do that10:51
lekernelterpstra: hi10:51
lekernelwhat you're looking for is there: http://git.serverraum.org/?p=mw/openocd-lm32.git;a=summary10:51
terpstrabtw, where can i find a "clean" copy of the milkymist lm32? i've fixed a few bugs in the copy i got from your tree and probably should give you the patches10:51
lekernelit's undocumented however10:51
lekerneland, afaik, not thoroughly tested10:52
terpstrathese things are not roadblocks ;)10:52
lekernelterpstra: hmm, there is no copy of the "milkymist lm32" other than in the milkymist github repository10:53
lekernelwhat kind of bugs have you fixed?10:53
terpstrathe jtag tweaks you guys did had problems with clock domains (for altera at least)10:53
terpstrai 'fixed it' by making it use the capture JTAG state instead of just grabbing data on e1dr10:54
terpstraand thus removed sensitivity to stuff that wasn't the clock10:54
terpstrathe other problem was that you couldn't flush the icache over jtag10:54
terpstrathe jtag write csr was just ignored10:54
terpstrathis is needed if you load your firmware over jtag (as i do) and then want the cpu to execute it10:55
terpstraalso i changed the register file10:55
terpstrayou had it using actual registers10:55
terpstrai switched it to use the positive edge EBR implementation10:55
terpstrawhich costs 2k of memory bits but saves like 1-1.5k LUTs10:55
lekernelmh, last time I checked Xst was able to synthesize the LM32 register file on distributed RAM10:55
terpstra(making the LM32 only 3k instead of 4.5k on cyclone3 and 1.5k on aria2)10:56
terpstrathe code i copied was still using lattice blackbox logic for this.. .?10:56
terpstrai switched it to inferred10:56
lekernelha, so you're not using the milkymist code I think... I stripped out all the lattice logic10:57
terpstranot all10:57
terpstraoh: i also pipelined the multiplier10:57
terpstrathat let me get it up to 175MHz10:57
Fallenouwow :)10:57
lekernelin cyclone?10:57
Fallenounice !10:57
terpstrayou stripped out a lot of the ram stuff in the i/d-cache10:57
terpstracyclone3 is 125MHz10:57
terpstraaria2 is 17510:57
lekernelah, yes :)10:57
lekernelthat's still pretty fast10:58
terpstrai am pretty happy with it10:58
lekerneleven without a multiplier at all spartan6 barely reaches 100MHz10:58
terpstrait seems to run stable (and quartus timequest was happy anyway)10:58
terpstrai have everything except DIV enabled10:58
terpstrathe DIV seems quite expensive for very poor performance gain :P10:59
lekernelwhere is the remaining lattice blackbox logic? i'm checking the code atm10:59
lekernelit's probably `ifdef'd out anyway, since Xst doesn't whine10:59
terpstrayou need dual port ram10:59
terpstrathat's why you didn't do it10:59
terpstrayou made a single port lm32_ram10:59
terpstrabut the register file needs dual port10:59
terpstralook in lm32_cpu.v11:00
terpstrasearch down to11:00
lekernellm32_ram is always supposed to be single port, no?11:00
terpstrasearch to: 'Register file instantiation as Pseudo-Dual Port EBRs.'11:00
terpstrathat code is disabled b/c you don't set:11:00
terpstra`define CFG_EBR_POSEDGE_REGISTER_FILE11:01
terpstrain your include.v11:01
terpstrathat saved me a lot of area and might be why mine is faster than yours11:01
terpstrai made a lm32_dp_ram.v11:01
terpstrafor inferring dual-port memory and plopped it on top of the lattice blackbox11:02
terpstrathey use 2x dual-port for the register file as follows:11:02
terpstraeach cycle, the target register in both is updated11:02
terpstraeach cycle, the source register r0 is read from the copy0 and r1 from copy111:02
terpstraso single-port won't cut it11:02
lekerneliirc now the register file is implemented on asynchronous distributed RAM. yeah, maybe putting it into the block RAM might improve things a bit11:02
terpstralike i said, it cut 150% to 100% area for me11:03
lekernelthough I doubt it would be as much as 125MHz11:03
lekernelyeah of course, if you had it on pure LUTs in the beginning, it becomes slow and bloated11:03
lekernelwith distributed RAM, it's not as bloated as pure LUTs11:03
terpstraafaik, that's what you're doing atm?11:03
terpstrayou're using the registers[] array11:03
Fallenouthe array if inferred in blockram i guess11:04
terpstra reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1];   // Register file11:04
terpstrathat didn't become inferred blockram11:04
terpstraand i doubt it can11:04
terpstrasince it's used with multiple access11:04
lekernelbecause the LUT becomes used as an optimized RAM11:04
lekerneli.e. the portion of the LUT that is normally used for configuration stores instead the RAM data11:04
lekernelit's a special mode of the Xilinx LUTs11:04
terpstrai've not used xilinx yet11:05
lekerneland, iirc, Xst infers this mode for the LM32 register file11:05
kristianpaul(125MHz yay !)11:05
terpstrakristianpaul, it gets slower once you hook the WB up to a crossbar11:05
terpstraatm my design only hits 124.6MHz (which is extremely frustrating)11:05
kristianpaulah :--/11:05
lekernelterpstra: still it'd be interesting to examine the possibility to map it to block RAM11:05
lekernelcould you send your patch to the mailing list, along with the jtag fixes?11:06
terpstralekernel, like i said, i just made an inferred dual port memory and plopped it in11:06
Fallenouplease share your code ;)11:06
terpstragive me a pointer to where your clean tree is11:06
terpstraand i'll break my tree into patches wrt. it11:06
lekernelcyclone 3 seems pretty fast anyway11:07
terpstra(*runs off to find documentation for git*)11:07
lekernelhow much % of it is used for LM32? and how much does your chip cost?11:07
terpstrai'm using the 'cyclone3 starter board'11:07
terpstrait was just lying around our office11:07
terpstrai don't know how much we paid for it11:08
terpstrai've heard pricing varies a lot based on who you buy it from though11:08
terpstramy design atm is 4.6k LUTs11:08
lekernelhttp://www.altera.com/products/devkits/altera/kit-cyc3-starter.html ?11:08
terpstraat 14% of chip11:08
lekernelhe, pretty good11:09
terpstrathat's the one11:09
terpstrawe also have a few aria2 PCIe board11:09
terpstraon the arria2 it was 1.5k LUTs -- or 1.5% area11:09
terpstra(ie: could fit tons of them on it)11:09
lekernelbut arria2 is expensive, no?11:09
terpstrai don't have to buy these things, so don't know ;)11:09
terpstrafor our SoC arria2 is the eventual end chip11:10
Fallenoucyclon3 starter kit seems a nice board :) not so expensive11:10
lekernelthe same design uses 3.4k Cyclone 3 LUTs and only 1.5k Arria2 LUTs?11:10
terpstraarria2 seems much smaller11:10
Fallenoudefinitely less expensive than spartan6 xilinx boards11:10
terpstrafatal: https://github.com/lekernel/milkymist/tree/master/cores/lm32/rtl/info/refs not found: did you run git update-server-info on the server?11:11
terpstrai'm not a git user11:12
lekernelyou should use git://github.com/lekernel/milkymist.git as git clone URL11:12
lekernelnot the HTTP link11:12
terpstrayou guys use pure verilog, yeah?11:14
terpstraour interconnect is all vhdl so i guess you don't want that11:14
rohuh. 200$ is surprisingly cheap for a develboard11:14
lekernelwhen we move to our own synthesis technology, it'll be easier if we have only one language :)11:14
terpstrait's quite nice to use, the cyclone311:15
rohterpstra: well.. does it have nicer tools than quartus ;)11:15
terpstrawhat's wrong with quartus?11:15
terpstrayou can still use joe and make ;)11:15
terpstragot a patch file with all the whitespace and/or warning-silencing edits removed11:17
terpstrabut it kinda rolls all the changes together11:17
terpstrawhere to send it?11:18
lekerneldevel at lists.milkymist.org11:18
rohterpstra: well.. its the same crap as xilinx tools.. in 'getting them' as well as 'installing them'11:18
rohthey are _huuuughe_ and the vendors are a pain in the ass with only for account users and stuff..11:19
lekernelroh: you are welcome to send me llhdl contributions ;)11:19
lekernellet's replace this crap11:20
rohlekernel: heh... first i need to be able to WRITE code in verilog. currently i am quite happy to make sense of it when reading. knowing electronics and C helps a lot tho11:21
rohmy last attemt to install ISE was prohibited by available diskspace *sigh*11:21
rohwhat the f*ck do they need 2-digit gbytes for?11:22
lekernelown copy of the C libraries, own copy of the C++ libraries, JVM, own copy of Perl, ....11:22
rohlast time i installed quartus i needed win32 for it and it crashed on a (guided) attempt to compile something.. i guess because it was a guide and code for another version or so... sigh.11:23
lekernelplus a ton of bloated pseudo-cross-platform libraries11:23
rohjvm? wtf?11:23
lekernelyeah, some parts of the xilinx toolchain are in java11:23
terpstraok, email sent11:23
rohif their licence wouldnt suck someone could make it _very_ small i guess.. removing all the stuff already packaged in the distro (if you got an os with packaging and not win32)11:23
lekernelalso some of their executables aren't stripped11:24
terpstrai suppose i should subscribe to this list11:24
lekernelterpstra: i'll moderate your message11:24
larscroh: i guess you are lukey that it doesn't bring its own apache with php11:24
lekernelterpstra: so, you're doing heavy ion research? interesting :)11:25
terpstrai appologize for writing the firmware loader in tcl.... altera still won't give me the headers to talk jtag via C11:26
terpstrathat's what GSI has done in the past11:26
rohlarsc: these would be actually small ;)11:26
terpstrawe will be producing positrons and stuff now11:26
terpstrawe need a softcore as part of the control system that runs the accelerator11:26
scrts`how much did You pay for that arriaII pci-e board?11:26
scrts`I am looking for a pci-e board :)11:27
lekernelterpstra: there's also Uwe Bonnes from the Institut für Kernphysik in Darmstadt who's doing similar things11:27
lekernelwith softcores I mean11:28
terpstramy colleague says we paid 1500EUR11:28
terpstrafor the PCIe11:28
lekernelhe's on the milkymist list11:28
terpstrabut that's the more expensive development one we use for prototyping11:28
wolfspraullekernel: do you have some Milkymist news I should mention in the qi february community update?11:29
lekernelwolfspraul: on http://en.qi-hardware.com/wiki/Community_news_2011-02-01 ?11:32
lekernelJTAG cable fix, power-up fix11:32
lekernelso, power-up fix11:34
wolfspraulI'll move Milkymist up (before NanoNote), we have to push it more :-)11:34
lekernelhe, I didn't see that http://en.qi-hardware.com/wiki/File:Sigemm1.jpg11:34
wolfspraulanything on the rtems or flickernoise side?11:34
lekernelflickernoise improvements: PDF-based online help system, GUI usability improvements (like mouse wheel scrolling support)11:35
lekernelon rtems, there has been some bugfixing on Ethernet11:35
lekernelbut it'd still need work11:35
Fallenouyes ethernet is improving, but there is much more to do11:36
wolfspraulok this is helpful11:36
lekernelwolfspraul: also you can post about the french linuxmag article that I released11:37
wolfspraulbut the article is a year old, no?11:37
terpstrathis openocd project is not affiliated with milkymist?11:37
lekernelwolfspraul: yeah, but it's a technical article anyway (on MM SoC)11:37
lekernelit's still valuable content I think11:38
lekernelsome people still don't get what mm soc is about11:38
wolfspraulwhy did you publish it now?11:38
wolfspraulyou had to wait 12 months?11:38
lekernelit was published on paper before11:38
wolfspraulso the news is 'after a 12 months freeze period, Sebastien was able to publish...'11:39
wolfspraulor I leave the freeze out, need to shorten it11:39
wolfspraulok I'll mention it11:39
lekerneljust leave the freeze out11:39
lekernelmost of the technical info in there is still accurate11:40
lekernelalso, mwalle posted some Linux patches in order to have clean bFLT binary support11:41
lekernelyou may want to put those forward, Linux support is often what rings bells in the open source community11:45
terpstrai wish i'd seen this file earlier -.-11:47
larsci'm hoping that i'll find some time this week to finally turn the kernel and uclibc patch into an actuall linux distro using openwrt11:47
terpstrawould've saved me quite some wirj\11:47
lekernelterpstra: openocd isn't part of milkymist, it's a generic JTAG debugger that mwalle (temporarily) forked and added milkymist support to11:48
terpstraso the jtag changes you guys made to the lm32 were actually working for you?11:49
lekernelas I said, this wasn't thoroughly tested11:49
lekernelbut at many parts of it worked, yes11:49
terpstrayou are using the uart to communicate with your debug rom11:50
terpstrai'd hoped to avoid doing that11:50
terpstrawhere is the rom that goes with this port?11:52
lekernelterpstra: https://github.com/lekernel/milkymist/tree/master/software/monitor11:52
terpstrawow. quite small!11:53
terpstrai'll look into it after lunch.11:53
terpstrathank you very much for all these links.11:53
terpstrai hope my patch might prove useful in speeding up your LM32 too :)11:54
lekernelhopefully :)11:56
lekernelbut meeting timing in mm soc is a bloody quagmire11:56
lekernelsometimes, _removing_ logic breaks timing11:56
lekerneljust because the placer's heuristic algorithm then picks the wrong numbers11:57
lekerneland so far I haven't really found a better way of getting things to work than to run multiple instances of the place and route on a multicore machine each with a different PRNG sequence11:59
lekerneluntil one happens to work11:59
roheh. how do you know which one 'works' ?12:00
lekernelthere's a timing model that tells you if the design is ok or not12:00
lekernelthis, of course, is also subject to bugs12:01
lekernelespecially with spartan6 it seems12:01
lekerneli've overclocked designs without problems by as much as one nanoseconds12:01
rohthe more i learn about fpga and their develtools.. the more frightend i am about the wicked state of affairs. man thats dirty and bloody.12:01
lekerneland, on the other hands, designs that were supposed to meet timing exhibited intermittent issues until I froze the FPGA to some -40C12:02
lekernelfortunately it's rare, but it happens12:03
lekernelbottom line, a good freeze spray is sometimes handy when you're tracking down weird FPGA bugs12:03
rohlekernel: hehe. yes. also when debugging other electronics.12:05
roheven on repairing analog electronics12:05
lekernelroh: all silicon compilers are dirty and bloody. you can read even better stories e.g. on http://deepchip.com/12:06
terpstralekernel, why are you using such a bad tool for place and route?12:20
terpstraif it's so unreliable, pick another12:20
lekernelthere's no other12:21
terpstraor is this the xilinx tools you speak about?12:21
lekernelyeah, it's the xilinx place and route12:21
terpstraquartus seems quite reliable when it comes to synthesis12:21
terpstraand it can show you nicely where and why your design is slow12:21
lekernelwell, I had my share of Altera bugs too12:22
terpstrai'm not exactly experienced with these things... only learned vhdl and verilog three months ago ;)12:22
lekernelwhile I think their software is slightly less bad than Xilinx's, I wouldn't be surprised if such p&r woes also happen with Altera12:23
terpstrayou mean the inconsistent timings that come out of placed and routed logic?12:24
terpstrasupposedly altera can use timing-driven synthesis to help here12:24
lekernelno, I'm talking about timing model bugs12:25
terpstrai see12:25
terpstrawell altera has two different timing analsys tools12:26
terpstrahopefully at least one of them will work ;)12:26
terpstra(tho so far i've only seen both work)12:26
lekernelthat sounds quite painful too :)12:26
terpstrathe newer chips use the newer tool "time quest"12:26
lekerneli'd say: let's simply develop our own open source timing engine12:26
terpstrathe older ones used some other tool12:26
terpstralekernel, i think you underestimate how hard it is to do this well12:27
lekerneloh, I never said it was easy12:27
terpstrait's my understanding also that the bitstream you need to program FPGAs is a closely guarded trade secret12:28
terpstraso making a new synthesis tool would ba a PITA12:28
lekerneli'll probably get the complete (reverse engineered) spartan6 xilinx bitstream format in my mailbox during the next weeks :)12:29
lekerneland btw, it's not that hard to reverse engineer12:29
terpstraare you seriously planning on building your own synthesis tool?12:30
lekernelI wouldn't say it's easy, but it's not impossible or super-hard either12:30
terpstrai didn't say it would be hard, i said it would be a PITA. expect lawsuits coming your way if you use that reverse engineered info.12:30
lekernelphew. that's what everyone says. but i've heard a lot of rumors and all turned out to be false12:30
terpstraas part of installing quartus, i agreed not to reverse engineer it12:30
terpstra(in the licence text(12:31
terpstradon't get me wrong, though: building an open source synthesis tool would be a great project!12:31
terpstrajust like gcc is the cornerstone of open source12:31
lekerneliirc the xilinx licenses prohibits decompilation and disassembly. the bitstream format is recovered using black box techniques12:31
lekernelthe guy runs the toolchain the normal way, and then uses custom binary analysis tools on the result12:32
lekerneland btw, I'm not even sure Xilinx would go after a project that produces bitstreams for their devices12:33
lekernelthere are tons of rumors depicting FPGA companies as "evil guys", but an astonishing amount of them are pure bullshit12:33
terpstrai've been pretty impressed by how open altera has been with me12:34
terpstrai asked them for the header files for their jtag client library12:34
terpstraand mentioned that an NDA would be a problem12:34
lekernelXilinx even provides (unsupported) lists of all the interconnect in their chips12:34
terpstra... and they sent me complete documentation and a whole whack of source12:34
lekerneli'm even writing a parser for them atm ;)12:35
lekernelthose are multi-GB text files12:35
lekernelwhat's missing is 1. timing information (this will be hard, probably need to build a chip characterization system) and 2. how this information relates to bitstream content (not extremely hard to find out)12:36
terpstrathis debug ROM is evil. r0!=0. bad. :)12:36
lekernelterpstra: it's done on purpose... and works nicely12:36
terpstrai know12:36
terpstrai was planning on doing it too ;)12:36
terpstrait's the only available register that one can smash to point to the register save region12:37
lekernelthe characterization system would probably involve building various ring oscillators with the elements to characterize in the loop12:37
lekernelthen measuring the resulting frequency12:37
lekerneland finally solving the system of equations to find out the timing property of each element12:38
lekernelthis sounds like a lot of fun12:38
terpstrawouldn't you just trace the signal from inputs to outputs?12:38
terpstrasome sort of graph traversal algorithm12:38
terpstrawith weights based on chip-specific timing information12:38
lekernelyes, but it's easier to do that automatically and on-chip with a ring oscillator12:38
terpstrawhy would you want to do timing analysis on-chip?12:38
lekerneloh, the purpose is to recover that timing information12:39
terpstrai'd rather be running it on my fat intel devel system12:39
terpstrasorry, i gotcha12:39
lekernelit's built into the xilinx software atm12:39
lekerneland we can either reverse engineer the software, or measure it ourselves12:39
terpstraso you want to make what amounts to a bitstream that can measure the delays in the chip12:39
lekernelimo the second technique is more fun, accurate and legal12:39
terpstraand then use that to feed into the timing analysis program12:39
terpstrayou would be able to account for per-chip variability that way12:40
lekernelyeah, we'll probably need to run measurements on many chips and at different voltages and temperatures12:40
lekernelbut it's easy. all it would need is a jtag probe and a on-board stable clock source12:40
terpstrain terms of open source synthesis tools12:40
lekernelthe rest is automated12:40
terpstrai'd be more interested in the front-end stuff12:41
lekernelthe front end stuff is already working to some extent12:41
terpstrayou do the necessary optimizations/etc already?12:42
lekernelthis works for example:12:42
lekernelno... I spent less than two months on that12:42
lekernelat first I focus on producing working netlists12:42
lekernelnot necessarily fully optimized12:42
lekernelthough it's already capable of using carry chains and such12:42
lekernelmissing optimizations are a good "random logic" LUT mapper (I'm thinking of using the BDS-PGA algorithm)12:43
terpstrai like the idea of a LLVM for hardware a lot12:43
lekernelFSM re-encoding12:43
lekerneland a couple of smaller things, like shift register extraction, large mux extraction, large comparator extraction, ...12:44
lekernelmost can be implemented with the current architecture as Mapkit "plug-ins"12:44
lekernelalso, there are a couple of things that the Verilog front end doesn't support, e.g. instantiations, parameters, case statements and generate12:45
lekernellots of work :p12:46
lekernelbut still not too bad for < 2 months12:46
terpstrai'm somewhat surprised no one else has started doing this already?12:46
lekernelwell, there have been attempts12:46
lekernelbut usually they all degenerate into sterile debate and often undue trolling towards FPGA companies12:46
lekerneland, sometimes, fail because of mere technical incompetence12:47
lekernelbut I think the main factor is trolling and other management problems12:47
terpstraif i had more time, i'd be interested in helping out12:48
terpstramaybe in a few months i'll be back12:48
lekernelhttp://www.fpgarelated.com/usenet/fpga/show/36355-1.php is a good example of what typically happens in this field12:49
lekerneland the funniest thing is JHDLBits never got squashed by Xilinx12:50
lekernelit's all rumors12:50
terpstraby not interfacing with their code at all12:51
terpstrabut building from bitstream+jtag up, you avoid a lot of the stickiness12:51
lekernelLLHDL puts out EDIF, which is a standard format...12:51
lekernelwhich is then read by the xilinx p&r (for now)12:52
lekernelLLHDL is just the front end, it doesn't do any physical implementation12:52
lekernelthis will be handled by a separate project (and now by the fpga vendor's tools, through the standard EDIF interface)12:53
terpstraso you can already run your compiled llhdl?12:53
terpstrathat's nice!12:53
lekernelyeah, the verilog file I posted works nicely on the MM1 board12:53
lekernelwith llhdl synthesis12:53
lekernelI expect that in some other two months, it'll be with open source antares p&r and bitstream generation :)12:54
terpstrado i understand this rom that on a breakpoint it saves everything to ram, reports via uart that its ready and then reads the offset (!) of the command to execute?12:58
lekernelmh... I don't know... mwalle wrote this12:59
terpstrayou guys are french, yeah?12:59
lekernelnot everyone13:00
lekernelactually most people here are German13:01
lekerneland I live in Berlin, though I'm French :)13:01
terpstrai think i understand this ROM enough now to use it. now to try and compile this openocd-lm32 :)13:01
terpstrai live in darmstadt, though i'm canadian13:01
lekernelhe, we can visit GSI?13:04
lekernelsounds fun :)13:05
terpstrathey have tour guides and everything13:05
lekernelI was at LHC last year and ILL this summer13:05
terpstrathen they lead you into the accelerator room, look the door, and turn on the beam!13:05
roh .oO(we need a particle accellerator at the camp!11!)13:05
rohmust-be for hackers this summer13:06
lekernelroh: we can take stuff out of that X-Ray system I told you about. last attempt stopped when I ran into the probably PCB-contaminated oil cooling system13:06
lekernelmaybe i'll come later with appropriate gloves etc.13:06
lekernelThe number of participants should exceed 10 persons and stay below a maximum of 60 persons.13:10
lekernelok, who's in?13:10
rohlekernel: ccc berlin does 'hackertours' sometimes.. maybe you should ask for participants there.13:13
terpstraif you do come to the GSI, let me know13:15
terpstrayou can meet the real hardware hackers here13:15
rohterpstra: bring people to the camp 2011 ;)13:15
rohwe always want to meet people working on the interresting stuff nobody else understands13:15
rohhttp://chaosradio.ccc.de/ctv113.html explains the camp13:16
scrts`whats the camp 2011? :)13:21
lekernelterpstra: i'm driving to Paris in May. Darmstadt is a very small detour.13:22
rohscrts`: 2 lines above your question13:27
lekernelroh:  btw, are there lectures there?13:27
lekernellike HAR13:27
rohlekernel: yes. ofcourse. also workshops.13:27
lekernelwell, from now on I'll avoid CCC workshops13:28
lekernelbut perhaps a LLHDL talk would be nice13:28
rohnaah. dont be a little girl...  self-organisation also doesnt work sometimes13:28
rohif you really want to do something.. just do. nobody will hinder you. you could even set up your own big tent if you like13:29
rohfrom a certain size up we ask to announce that in advance for planning and reserving the space13:29
lekernelroh: do they send a cfp and when?13:31
rohwe are working on that the coming weeks13:32
terpstraopenocd-lm32 doesn't build cleanly as version.texi is missing13:32
terpstragit add? :)13:32
rohi think for the camp it will be rather a 'call for participation' since people really seldomy send in papers lately13:32
lekernelI must say that after the milkymist workshop quagmire, this doesn't really encourage me to submit :)13:34
terpstrawhich one of you is sebastien?13:34
lekernelit's me13:35
terpstraok :)13:35
terpstrai realized i forgot to send you lm32_dp_ram.v -.-13:35
lekernelsend it to the list13:35
lekernelopen reviews and horizontal communication are good13:36
rohlekernel: maybe you should rather submit a talk and do the workshop less planned13:42
terpstralm32> load milkymist/software/monitor/monitor.elf13:43
terpstraCapturing the CPU at address 0x0: done13:43
terpstraLoading 0x000054+0x00554 to 0x1000000013:43
terpstra section .text: 1364 bytes - complete13:43
terpstraReleasing CPU: done13:43
rohthat always worked good afaik. also we know that the workshop-orga was not good at the congress (there wasnt any) and we need to get better there (wanna help with it? ;)13:43
terpstradoh.  my initial DEBA dosen't match13:44
lekernelwell, maybe :)13:45
lekernelterpstra: out of those 1.5K LUTs on Arria2, how many of those LUTs use the "fracturing" feature?13:58
terpstrai don't know what that is ;)13:58
lekerneli'm quite amazed that this FPGA architecture cuts the LUT count in more than half13:58
lekerneland I even suspect some figure manipulation ;)13:58
terpstrawhat is the fracturing feature?13:59
lekernelmake two LUTs with one13:59
terpstrai've never seen it mentioned in the consumed resources reports13:59
lekernelwith fewer inputs each13:59
terpstrai'll copy-paste the relevant bits from the report14:00
terpstra; Family                             ; Cyclone III                                   ;14:01
terpstra; Device                             ; EP3C25F324C6                                  ;14:01
terpstra; Timing Models                      ; Final                                         ;14:01
terpstra; Total logic elements               ; 3,571 / 24,624 ( 15 % )                       ;14:01
terpstra;     Total combinational functions  ; 3,330 / 24,624 ( 14 % )                       ;14:01
terpstra;     Dedicated logic registers      ; 1,650 / 24,624 ( 7 % )                        ;14:01
terpstra; Total registers                    ; 1650                                          ;14:02
terpstrathat's for the cyclone314:02
terpstrai'll rebuild it now for arria214:02
lekernelah, it's "logic elements"14:02
lekernelso a LUT fractured in two would count as one14:02
lekernelwho, are they shipping cyclone 5 now, or is it the same vaporware as xilinx 7 series?14:06
terpstrai can't compile for arria2 under linux14:06
terpstrai forgot14:06
lekernelso, you see, software problems with altera too :)14:06
terpstrathe stupid parallel port dongle only works under windows :P14:07
terpstrawell, if we'd bought linux-friendly licences...14:07
terpstrait will let me target a generic arria214:07
terpstrabut that won't give an accurate fill %age and it picks the smallest that works14:08
terpstra(i don't want to reboot)14:08
lekernelkk never mind14:08
terpstra; Family                            ; Arria II GX                                   ;14:08
terpstra; Met timing requirements           ; N/A                                           ;14:08
terpstra; Logic utilization                 ; N/A                                           ;14:08
terpstra;     Combinational ALUTs           ; 1,805                                         ;14:08
terpstra;     Memory ALUTs                  ; 0                                             ;14:08
terpstra;     Dedicated logic registers     ; 1,650                                         ;14:08
terpstra; Total registers                   ; 1650                                          ;14:08
terpstra; Total pins                        ; 4                                             ;14:08
terpstra; Total virtual pins                ; 0                                             ;14:08
terpstra; Total block memory bits           ; 126,976                                       ;14:08
terpstrahere it talks about ALUTs instead of logic elements14:09
lekernelseems detailed here: http://www.altera.com/literature/wp/wpstxiiple.pdf14:11
terpstra... lol at figure 114:12
terpstrain my design, i use a full crossbar interconnect14:14
terpstraso their little example showing a 2* savings is somewhat relevant14:14
terpstrabut that's not the majority of the used area ...14:14
lekernel"The benchmark comparison uses 80 real customer designs." ...does the Altera software includes, like the Xilinx one, a mandatory phone home "feature" to gather those statistics?14:15
terpstrait's opt-in14:16
terpstrabut, yes14:16
lekernelif you take the free of charge version of the xilinx tool, it's always enabled and you can't "opt out"14:17
terpstrathe web edition version of quartus is quite nice14:17
terpstrai use it under linux even though i have a fully licenced windows version14:17
lekernelwell, the way to opt out anyway is to delete its curl library, so it isn't too hard14:17
terpstrai just miss the signaltap2 logic analyzer (which to be fair is quite essential)14:18
terpstraand synthesis to the higher end fpgas14:18
lekernelyeah... one should design an open replacement to signaltap/chipscope14:18
lekernelpreferably platform independent14:18
terpstradoesn't seem that hard a task really14:18
lekernelno, it isn't14:18
terpstrait could be done as a compiler pass in your llhdl14:19
terpstrajust a bit of tooling of the llhdl to add hooks and a capture logic14:19
lekernelwell, in LLHDL you can write the IR to files and manipulate that in custom applications14:19
lekernelyou won't even need to touch the core code, just develop an independent utility14:19
terpstrai doubt that would work as cleanly as you envision14:20
terpstrayou need access to the original symbol names and hierarhcy14:20
terpstraotherwise the user won't be able to say what signals he wants14:20
lekernelthose are accessible from the "external" flow14:20
terpstra(i assume your llhdl will perform optimizations which rename the signals during their work)14:20
lekernelonly in the last passes14:20
lekernelbut you can hook before aht14:20
terpstraregardless, not a difficult task14:21
lekernelthe first passes compile Verilog (and maybe VHDL) without any optimization14:21
terpstrajust some work14:21
lekerneland directly write LLDHL interchange files that you could pass to linker, optimizers and mappers14:21
lekernelor fancy things like logic analyzer insertion utilities14:21
terpstraanyway, the moral of that document you sent me seems to be this:14:22
terpstrastratix 2 ALUTs are bigger than stratix 1 / cyclone 3 LEs14:22
terpstraso it's apples and oranges14:22
terpstradon't suppose you know where the openocd.cfg for the lm32 is?14:25
lekerneliirc there were some threads on the mailing list about that some months ago14:27
lekernelbut i'm not sure14:27
larscterpstra: thats what i have in my milkymist openocd.cfg: http://pastebin.com/ghq1wVKU14:33
terpstrait claims to support usb-blaster14:34
terpstrabut doesn't seem to work14:34
lekernellarsc: does openocd work for you?14:35
lekernel(I have never tried it)14:35
larsclekernel: it was unstable the last time i tried it14:35
larscto unstable to be useful14:36
terpstramy tcl script is stable, but doesn't talk to gdb :/14:36
terpstrafairly certain that my problem is that openocd doesn't support usb-blaster properly, despite it's claim to the contrary14:37
terpstraError: IR capture error at bit 2, saw 0x3FFFFFFFFFFFFD55 not 0x...314:37
larscterpstra: you enabled it in ./configure and changed the interface in the config file?14:38
terpstragot it14:39
terpstraInfo : JTAG tap: ep3c25f324.tap tap/device found: 0x020f30dd (mfg: 0x06e, part: 0x20f3, ver: 0x0)14:39
terpstraaha :)14:42
terpstra        if (strcmp(variant, "xc6s") == 0)14:42
terpstra        {14:42
terpstraneeds some generalization ;)14:42
lekernelterpstra: feel free to send contribs to the same ML ;)14:44
terpstradon't have it working yet14:44
terpstrait sees the jtag chain, but not the lm3214:44
terpstrabut will get there :)14:45
terpstrai also know my jtag chain is perfectly stable as i've loaded and read multiple MBs of firmware with my tcl tool14:45
terpstraso whatever problems i have are just openocd specific, which should help narrow it down14:45
lekernelterpstra: how do you make 92+ uranium?!15:15
terpstradon't ask me stuff like that15:15
terpstrai just work here!15:15
lekernelwell, you happen to make this stuff at GSI :)15:15
terpstrathe physicists make the machine go15:16
lekernelthe GSI website says "Fully stripped U92+ ions from the heavy-ion synchrotron SIS"15:16
terpstrathey make it go round and roung15:16
terpstravroom vroom15:16
lekernelbut from what I know about ion sources, it's pretty difficult to strip more than a dozen electrons off an atom15:16
lekernelso 92... wow15:17
terpstra(they strip the ions by hitting them through some sort of thin metal i believe)15:17
terpstraand they do it multiple times15:17
lekernelmh, maybe... must be very small quantities then15:17
terpstrawell, they start with very big quantities15:17
terpstraand they get smaller and smaller ;)15:17
terpstrai've noticed a strange behaviour with the lm3215:21
terpstraissuing a 'break' over jtag has no affect until you do either a uart recv or memory read15:21
terpstrawtf :P15:21
terpstramy led blink keeps running until then15:22
lekernelMarcus Erlandsson, Chief Technology Officer and Founder, OpenCores16:37
lekernelAbstract: Open-source hardware IP-cores is today the only efficient way of developing the next generation of products. A problem today with product development is that when product complexity increases, the verification workload increases exponentially, which leads to significant higher development costs. Open-source hardware enables companies to significantly reduce verification costs and therefore allow a more cost-effective developme16:37
lekernelnt method.16:37
lekerneloh my...16:37
lekernelthere are more bugs in a opencores project than in the average rainforest, and they invite _him_ to talk about _verification_16:39
lekerneloh, and Arduino "the father of Open Source hardware"16:40
lekernelok, got it16:40
lekernelI wonder what percentage of that opencores bullshit talk is delusions and what is outright lies to please some investor or (poor) ORSoC customer16:47
wpwraklekernel: maybe you should speak at such conferences, too ? ;-)16:49
lekernelI don't know16:49
kristianpauli agree with wpwrak16:50
wpwrakshow people that there's life beyond the bovine feces :)16:51
lekerneldo they want to know? everyone feels good about blinking LEDs...16:54
lekernelthe only way to pull that off is to make big lectures at large/central conferences, preferably where there are lots of journalists and well-known people16:57
lekernelotherwise you're just gesticulating16:58
tuxbrain_awaylekernel: If it wasn't for you and for your work I had still part of this bovine feces.... well in fact I'm still there but at least you let me know there are higher grounds out there to walktrough time to time :)16:59
kristianpaulbovine = moo ? ;-)17:08
scrtshm, there are workng cores on opencores!17:16
scrtsI mean exists17:16
lekernelyeah, some 0.1%, sadly not including their flagship openrisc17:19
lekernelhow many products can you count that reliably use opencores IPs? except the cases where ORSoC claims one is used for "a large customer" which is never named?17:24
lekernelthat, and the "tracking everything" e.g. compulsory registration - about which they have double standards, they whine because lattice does the same - "because download statistics are essential to build credibility" (well, they should quit FPGAs and do lolcats and pr0n then)17:27
kristianpaullekernel: usrp2 i think uses zpu, not sure is that is on opencores17:29
lekernelzpu is on opencores, and zpu is crap17:29
lekernelwell, it's not an "official" opencores project17:29
kristianpaulthat 0.1% is your sdram controller? ;-)17:29
kristianpaulI saw it on opencores last tiem..17:30
kristianpaulalso navre17:30
lekernelnah, there are also some other decent designs there - aeMB for example17:30
kristianpaulwho else17:30
terpstrahey, jumping in here17:30
terpstracould you be more specific in your rant against openrisc and zpu :)17:30
lekernelwell, openrisc uses 3 times as many LUTs as LM32 for half the speed17:31
kristianpaulah, i remenber you are benchmarking those too, isnt terpstra ?17:31
terpstrai already more-or-less rejected openrisc as fatter than the leon3 with less functionality17:32
lekerneland, last time I checked, the design contained latches17:32
terpstrabut thought maybe you lot had more to say17:32
lekernelwhich are 1. surprising in a design I thought would be synchronous and 2. undocumented17:32
terpstrasome people at CERN really like the ZPU and i need more ammunition against it17:32
lekernelso I guess they come from the usual beginner's HDL pitfall17:33
kristianpaulyou fint the right place for that ;-)17:33
terpstrafound* ;)17:33
kristianpauloh, sorry17:33
lekernelI concede the ZPU isn't as crappy as OpenRISC, it's only problem is it's ridiculously slow17:33
kristianpaulwhat are doing with zpu at CERN?17:33
terpstrasame thing we are looking at the LM32 for17:33
terpstrause to run DHCP/ARP/PTP inside a timing controller to coordinate devices17:34
kristianpaulzpu have his own ethernet controller?17:34
terpstrathey like the ZPU because it's small. and it is. about 1/3rd the LM3217:34
lekernelthat's not counting the microcode ROM17:34
terpstrathe ethernet core will be a custom wishbone device from us17:34
lekernelthough it can be OK in a FPGA if you have spare block RAMs you wouldn't use otherwise17:35
terpstrathe microcode is less than 4k i think?17:35
terpstrausing a LM32 means you have fat icache and dcache17:35
terpstrawhich clock in at more17:35
lekernel4K is already a lot of area in an ASIC17:35
lekernelyou can disable the LM32 caches, can't you?17:36
terpstrain theory17:36
lekerneland it still would be faster than ZPU17:36
terpstrain practice, without icache you have no JTAG17:36
scrtslekernel, regarding question about used cores from opencores: my collegues use i2c core from opencores in our company, he said it works :)17:36
terpstraspeed is clearly in favour of the LM32... but we don't need soooo much speed from something just running dhcp/arp/etc17:36
lekernelterpstra: there's also the navre (AVR core) that I made for the USB controller17:37
terpstrai guess i could fix jtag for the lm32 without icache. it does seem strange that it doesn't have the hooks in the instruction_unit.v17:37
terpstrai have that in my list... i rejected it, because ...17:37
lekerneliirc it's some 1k Spartan-6 LUTs17:38
terpstrathings i listed against navre: only 1 committer/he could die (i guess that's you), self-reported status: beta, # of pages documentation: 0, tested # of FPGAs: 2, debug support/JTAG: no, no wishbone bus17:39
lekernelwell, yes. I only wanted those damn USB ports to work, not make a softcore17:40
lekernelunfortunately they all were unusable17:40
terpstrait was 1k LUTs on an arria217:40
terpstrafor the navre17:40
terpstracompared to 2-3k for the LM3217:40
kristianpaulterpstra: howfast is zpu i  your cyclone?17:40
terpstraand 500 for the ZPU17:40
terpstramy table must be wrong17:41
terpstrait says 300MHz17:41
terpstrabut i don't believe that17:41
lekernelseriously ZPU is super-slow. but if you can live with that slowness, good for you17:41
kristianpaulwhat? ;)17:41
lekerneloh, it's perhaps really 300MHz17:41
terpstrathe instructions do almost nothing tho17:41
lekernelbut ZPU takes some 50-100 cycles to do what another processor would do in one17:41
terpstrathis was all timed on an arria217:41
terpstrawhere LM32 is 17517:41
terpstraso it's 'possible'17:42
lekernelyeah, I'm not surprised17:42
lekernelin terms of clock speed, ZPU was also very fast for me17:42
terpstrai haven't done an in-depth test of the ZPU yet tho17:42
terpstraso take those #s with a grain of saly17:42
terpstrathe leon3 is pretty nice too17:42
lekernelso your 300MHz ZPU might perform like a 3MHz LM3217:42
terpstrathe code is hideous tho17:43
lekernelmaybe even worse, depending on code17:43
terpstrai know the ZPU is much slower than the LM3217:43
terpstrabut is that the only bad thing i can say?17:43
terpstrai've seen several implementations of the ZPU floating around17:43
terpstrado any of them have JTAG?17:43
terpstrai didn't find any17:43
lekernelif you do the speed/LUT ratio, the ZPU doesn't look that good17:43
terpstramy table is at the bottom of this page btw:17:44
terpstrait's not 100% up-to-date tho17:44
lekernelha, funny I posted the OHWR link on the mailing list a few days ago17:44
rjeffriesis there a qi-bot log for this channel? URL pls?17:44
lekernelrjeffries: it's in the topic17:45
kristianpaulrjeffries: en.qi-hardware.com/mmlogs17:45
rjeffriesin smuxi the topic seems hidden17:45
lekernelterpstra: and no, I didn't find any ZPU with JTAG17:45
lekernelafaik only LM32 and LEON3 have it17:45
terpstrathe 'documentation' made vague promises about jtag, is all17:46
terpstraopenrisc too17:46
kristianpaulterpstra: typo latticemico2317:46
lekernelopenrisc is a no-go17:46
terpstraat least via simulation17:46
lekerneldo you really trust something from people who have undocumented latches in their design?17:46
kristianpaulI still wonder how leon3 can be shiped to a spacecraft17:47
lekernelkristianpaul: leon3 is a good design17:47
terpstrathe code is pretty awful, but i guess very well tested17:47
terpstraand they have a redundant version17:47
lekernelyeah, except the coding style  :)17:47
terpstrawhere any single bit error in the chip is corrected17:47
terpstrathat's something no other softcore can do afaik17:47
kristianpaulredundtant is a good point :-)17:47
terpstraso cosmic rays != dead spaceship17:48
terpstraplus it has a fully working MMU17:48
terpstrathat's the big downside to the LM3217:48
lekernelyeah... only softcore to date which have it iirc17:48
terpstraopenrisc has MMU17:48
lekerneland please don't tell me about openrisc, I even managed to get the orsoc people to admit it doesn't work17:48
kristianpaulare you planing run linux on zpu?17:48
terpstra(and several closed source ones)17:48
scrtsmicroblaze? nios? :)17:48
terpstranios is closed ;)17:49
terpstrakristianpaul, no17:49
terpstrai hope!17:49
terpstraat least you lot have gotten uclinux to work already on lm3217:49
terpstraso it's less risky even with our own SoC than the ZPU in that regard17:49
scrtsbtw, noone ever tried to add MMU tu LM32?17:49
terpstranot as far as i know17:50
terpstrai actually think you could probably make a wishbone MMU adapter ;)17:50
lekernelterpstra: here's a more accurate openrisc project page: http://www.beyondsemi.com/page/products/processor_cores/openrisc17:50
lekernelmade by Damjan Lampret, the original Openrisc developer17:50
terpstralekernel, is that for real?17:51
lekernelof course it is :)17:51
terpstrahow is it still listed as the 'flagship product' of opencores??17:51
kristianpaullekernel: you mentioned a ppc softcore some time ago, what is it?17:51
lekernelbasically, Damjan took the personal challenge to build a CPU, and was somehow sucessful at it17:51
lekernelthat became the openrisc, but it was a "draft" design17:51
lekernelthen he gave up his open source hardware activities and went on to found Beyond Semi, with a complete redesign of the CPU17:52
kristianpaulterpstra: (flagship product) asic proven, already made baords for it,i bet some marketing too17:52
lekernelsince then, Opencores and Openrisc have been taken over by ORSoC, but they barely did anything to improve OpenRISC17:52
scrtskristianpaul that ppc softcore, isn't it LEON3?17:52
scrtsor LEON4 now afaik17:52
terpstraat any rate, openrisc is pretty much inferior to the leon3 in every way17:52
lekernelso that's what it is, a zombie draft design17:53
terpstraso it was never a serious contender17:53
kristianpaulscrts:i want to confirm ;-)17:53
scrtsit is a confirm :)17:53
lekernelyou can find some untold Opencores stories now and then...17:54
lekernelyup. leon3 is a lot more serious than openrisc. not only technically-wise17:55
kristianpaulI guess moxiecpu is not ready for production yet..17:55
lekernelmoxie looks promising, but it's not finished yet17:56
terpstrawhat's this about moxie saying WB doesn't do pipelined reads/writes?17:57
terpstraB.4 supports that just fine17:57
lekernelB.4 was released after Moxie development began I think17:58
terpstranot so hard to refactor17:58
terpstraour LM32 speaks B.4 :)17:58
lekerneldunno. maybe lack of time. moxie has been moving rather slowly17:58
lekernelah? interesting :)17:59
terpstrawhat i don't much like about B.4 is you can't tell ahead of time if it will pay off to do a burst transfer17:59
terpstrai read someone's thesis in the milkymist project and they talk about their SDRAM controller always doing bursts17:59
terpstraand that's fine17:59
terpstrabut it would be nice if you had some warning still in pipelined mode that sequential access is coming up17:59
terpstraso as not to waste the work18:00
lekernelwell, for the SDRAM, going out of burst mode requires a lengthy reload of the mode register18:00
lekerneliirc you can't do isolated single-word transfers18:00
terpstrabut for SRAM, say, would be nice.18:01
lekerneland newer SDRAM chips do not support non-burst mode18:01
terpstraanyway, not a deal breaker18:01
terpstrawe are using WB4 and that's not up to me18:01
lekernelalso, doing those optimizations need extra logic. need to determine if it's worth the deal :)18:01
lekernel(and development+debug time too)18:02
lekernelthere is something that allows you to explore this design space in high level simulations but for CPUs only18:04
lekernelhttp://www.virtutech.com/products/ I think18:04
lekernel(it's proprietary w/license fee)18:04
lekernelbut you can simulate some software and tune the number of CPU pipeline stages, enable/disable out of order execution, make the CPU superscalar with different issue widths, etc.18:05
lekerneland it would tell you in minutes how fast your software would go18:05
terpstranios has such configurability as well18:05
lekernelyup. but you need to go through a lengthy logic synthesis and, for unimplemented features, weeks or more of development time18:06
terpstraso, i guess i have finally figured out why openocd doesn't work for me18:07
terpstrait uses the usb blaster jtag directly18:07
terpstrato access jtag devices in the core logic you need to go through the 'jtag sld hub' indirection18:08
terpstraand openocd doesn't know how18:08
terpstraguess i have to teach it. :-/18:08
lekernelscrts: we _might_ participate in GSoC this year. it could _maybe_ be a good opportunity to get that LM32 MMU done18:11
roheeh. wasnt LEON softcores sparc?18:13
scrtsheh, would be cool :)18:13
terpstraroh, yes18:13
terpstraleon* is sparc compatible18:13
terpstraand thus rather fat ;)18:13
rohjap. http://en.wikipedia.org/wiki/LEON18:14
terpstrait takes just hours to get linux running on your fpga tho18:14
terpstrawhich is pretty nice18:14
lekernelI never managed to get it to work... the LEON3/GRLIB code breaks Xst all the time18:15
lekernelthe answer was "use synplify"18:15
terpstrawell, we only have altera chips18:15
terpstrathey all works ;)18:15
terpstralekernel, please don't commit my jtag patch to your tree just yet18:16
terpstrai may need to tweak it a tad bit for openocd yet18:16
terpstrait's a real shame there are only 2 unused opcodes in the LM3218:19
terpstrathat one of them is 42 softens the blow, i suppose18:20
lekernelyup... maybe they did that so the instructions can be decoded with few levels of logic18:21
terpstrait's definitely why18:21
terpstrajust a shame that you can't add much to it18:22
terpstrayou guys hooked up some odd vector floating point processor to it, yeah?18:22
lekernelyeah, but it's only using DMA buffers and CSRs18:22
lekernelno special CPU interface18:22
terpstrai want to add 'branch both ways' :)18:23
kristianpauloh, Etherbone just uses UDP for sending data..18:25
terpstrakristianpaul, yup18:26
terpstrawe assume a reliable medium18:27
terpstra(which we will have)18:27
kristianpaulSo what you to dont lost packages?18:27
kristianpaulah, assume..18:27
terpstrawe have FEC at the ethernet layer18:27
kristianpaulYou made your own swcihes/hubs ?18:28
kristianpaulWhat is FEC?18:28
terpstraforward error correction18:28
terpstrathe main reason for our custom network cards will be to get the clocks phase aligned to much better than 8ns18:29
lekernelterpstra: what is your system doing, exactly?18:29
terpstraso we have distributed and precise timing18:29
kristianpaulYour work sounds amazing :-)18:30
terpstrait's not really my work18:30
terpstrait's the groups work18:30
terpstralekernel, we need to control devices that direct the beam18:30
terpstralight moves quite fast18:30
kristianpaulah, WhiteRabbit is the Swich and the zpu will go in there?18:30
terpstraso we need the devices to be precisely coordinated18:30
terpstrakristianpaul, correct18:31
kristianpaulgroups work, yes18:31
terpstraalso in the endpoints18:31
terpstrathe ZPU is just what the CERN guys have been messing around with18:31
kristianpauls/zpu/lm32 ;-)18:31
rohtoo bad the stuff from maintech is closed http://www.maintech.de/produkte/ip-cores/18:31
rohbut well.. i guess thats their cashcow18:31
terpstrathat would be pretty cool :)18:31
terpstrabefore a really big open hardware revolution can begin---where vendors end up opensourcing b/c they used quality opensource IPcores ... we need a gcc for hardware.18:32
Action: terpstra looks at lekernel.18:32
rohgcc? naaah. someting free and open.. just not so bitrotten ;) better compare it to clang18:33
terpstragcc's bitrot is the proof of its success ;)18:33
rohand a problem for everybody wanting to do fancy experiments and develop new stuff for compilers18:34
terpstrasure, llvm is great18:34
terpstrabut if there had not been gcc, i doubt there'd have been llvm18:34
roha friend of mine will travel to nasa soon.. and give a talk at JPL about his 'theorem proover'18:35
terpstraalso know as an ML compiler? ;)18:35
rohsure. my guess is gcc will stay a macroassembler, while llvm will be the future of c compilers18:36
rohand a backend for lots of other languages18:36
terpstraat this point, that's a pretty safe "guess" to make :)18:36
kristianpaulall altera?, "Virtex 6 GTX simulation (Nikhef)." :-)18:37
terpstracern uses xilinx18:37
terpstrawe use altera18:37
terpstraso our stuff has to work on both18:37
lekernelit'll be used at CERN as well?18:39
terpstrathe LHC18:39
lekernelmh? I thought they were done with the design18:40
terpstrato be honest, i'm not entirely clear why they need it either18:40
terpstrawe're still in the design phase for the new accelerator here18:40
terpstrai've even heard that want to use it for their RF devices18:40
terpstrawhich seems quite perplexing!18:40
Action: kristianpaul reads http://silicone.homelinux.org/category/electronics/open-source-cpu/18:44
lekernelbye, thanks for passing by!18:49
kristianpaulyeah :-)18:49
Action: kristianpaul imagines if *RF* devices at CERN have a ohwr like project 18:52
lekernelkristianpaul: there is a surprising amount of this stuff being published. only you need to go looking for it18:53
kristianpaullekernel: it seems, i still amazed with ohwr18:55
antgreenlekernel: re: "moxie looks promising, but it's not finished yet". Had to take long break.  Back at it this week!19:11
antgreenas soon as I wrap up the libffi 3.0.10 release.19:13
antgreenwhat is Antares?20:05
antgreenoh, a mentor spin-off20:06
lekernelused to20:07
lekernelbut it no longer exists... this refers to https://github.com/lekernel/antares20:07
antgreenyou are evicting xilinx's tools from your workflow?20:08
lekernelbut it will take time20:09
antgreeneverything worthwhile takes time!20:09
antgreencool stuff.20:09
FallenouApplications for mentoring organization for gsoc are now being accepted20:49
lekernelyup. Jon is taking care of it this year21:24
lekernelafter last year's experience I'm not that much into applying myself21:25
mwalleterpstra: (debug rom) bascially thats a reverse engineered version of lattice original rom, with some tweaks regarding its size and added 16 bit and 32 bit access22:18
mwalleterpstra: (openocd) my lm32 port is wip (at least it was in progress .. ;) it should be at least possible to set some breakpoints and stepping22:21
mwalleterpstra: BREAK is sent as a JTAG DP (lattice calls it debug protocol, the real jtag commands, not the JTAG UART), isnt it?22:26
mwalleso i guess it should jump to DEBA right after issuing the command22:27
mwalleterpstra: (jtag core) iirc i just coded the (xilinx) jtag core according to xilinx schematics in some user guide. i dont know for sure if capture and reset are synchronous to tck for the xilinx BSCAN cell22:31
mwallegn8 :)22:34
--- Tue Mar 1 201100:00

Generated by irclog2html.py 2.9.2 by Marius Gedminas - find it at mg.pov.lt!