#milkymist IRC log for Monday, 2011-02-21

kristianpaulI tried gtkterm also...00:00
kristianpaulThe only way i got nice console output from the mm1 is when running something from flterm..00:00
Fallenouyes because of the \r policy00:00
kristianpaul\r ?00:01
Fallenoumilkymist just sends \n and no \r00:01
kristianpaulhmm00:01
Fallenouso you get horrible outputs from minicom or screen00:01
kristianpaulSo the only way is hack flterm to be a console?00:01
Fallenoumaybe you can try to set up your software to add extra \r to the \n00:01
kristianpaulor it is already a console'00:01
kristianpaulokk00:01
Fallenouflterm and gtkterm work well because they add extra \r00:02
kristianpaulFallenou: can you please upload and upload a file about 1Mb to flicernoise00:02
kristianpaulremenber create a user for you in the settings menu00:02
kristianpaulgtkterm dint worked..00:02
FallenouThe thing is I cannot use the GUI00:02
Fallenousince I have the weird mouse problem00:02
kristianpaulahh the mouse thing..00:02
Fallenouyes :(00:02
kristianpaulwell00:02
kristianpaulone more bug to the list..00:02
kristianpaulNow no warning..00:03
Fallenouyep it seems I am the only one to get this bug00:03
Fallenouam I ?00:03
kristianpaulnot wait i dont mean the other gui bug ;-)00:03
kristianpaulwas talking about send big (Mb) files from flicernoise to host..00:04
kristianpaulbut i need do more tests00:04
kristianpaulFallenou: can i create a filesystem using ram in rtems?00:04
Fallenoua ramfs ?00:05
Fallenouyes I think so00:05
kristianpaulyeah something like that00:05
Fallenouit is IMFS I think00:05
Fallenouhttp://www.rtems.com/wiki/index.php/File_Systems00:05
kristianpaulgood00:05
kristianpaulminiIMFS00:06
Fallenoudoesn't seem to be very documented00:06
Fallenoui would try IMFS first :)00:06
kristianpaulThis chapter should be written after the IMFS chapter is completed and describe the im-00:06
kristianpaulplementation of the mini-IMFS.00:07
kristianpaul:p00:07
Fallenouthere is also RAM disk in the block device section00:07
kristianpaulalready?00:08
kristianpaulflickernoise**00:08
kristianpaulFallenou: You already tried NFS?00:08
Fallenouno never00:10
kristianpaulhmm so i need learn doc ;-)00:10
Fallenouthere is something about how to mount nfs on flickernoise IIRC on milkymist wiki00:10
kristianpaulyeah?00:11
kristianpauli looked for nfs using mediawiki and got nothing..00:11
kristianpaullink?00:11
FallenouI searched and found nothing00:12
FallenouI must have dreamed00:12
kristianpaulhehe00:12
Fallenousorry00:12
kristianpaulnp00:12
kristianpaulah yes, gtkterm works nice with mm100:13
Fallenoubtw mount ip_address:/path /mountpoint should work00:15
Fallenouin rtems shell00:15
Fallenouhttp://www.rtems.org/irclogs/html/2010/rtems-42.html00:15
Fallenoutry mount -L after00:16
Fallenouin the irc log sebastien had it working with this command00:16
kristianpaulI think i have troubles mouting last time... but anyway if fail i'll writ to rtems list for help :-)00:16
kristianpaulah logs :-)00:16
FallenouI think nfs is working00:17
Fallenoutry some wireshark while doing the mount00:18
kristianpauloh yes, even for a ping i do :-)00:18
Fallenougn800:42
kristianpaullate or sooner first question about llvm port :-)01:08
kristianpaulweird, i got same Error: SC = 27 with or without memory card inserted..01:21
adamw_lekernel, http://tw.mouser.com/Semiconductors/Power-Management-ICs/Supervisory-Circuits/_/N-wnws?Ns=Package+%2f+Case|1&No=25&P=1z0wa6wZ1z0vllt01:57
adamw_i've still not decided to use which one. but I'd prefer to pick up SOT23-3 package, it's quite hard now to pick a suitable open-drain with SOT23-3 with specified delay time said over 140ms.02:00
adamw_I am still finding..if you have new idea, u can just tell me. ;-)02:01
lekernelmwalle: where did you see those div/mod opcodes?11:33
Fallenoulekernel: to mount a nfs FS from flickernoise shell, is the command mount -t nfs 192.168.0.X:/path /nfs ?11:35
Fallenouwith a previous mkdir /nfs11:35
Fallenou?11:35
lekernelyes11:35
Fallenouok11:35
Fallenoui have a pool error in qemu :x11:36
Fallenouand system hangs11:36
Fallenouan assert fails11:36
Fallenouil rtems code11:36
Fallenouin*11:36
Fallenouwhen trying to mount a nfs11:36
Fallenouhave you ever had this error ?11:37
lekernelFallenou: no11:52
lekerneladamw_: use whatever package, I don't mind if it's not SOT23... or would a bigger package cause PCB layout problems?11:52
lekernelfyi I have already used the MAX6303, but it's 8-SOIC11:55
adamw_lekernel, the part shows up Non-stocked or  Factory Stock Available on Mouser, I won't pick up.11:55
adamw_ha...good.11:56
lekernelwell, I also don't know if the MAX6303 characteristics are good for us11:56
adamw_i used http://downloads.qi-hardware.com/hardware/qi_avt2/v1.0/datasheet/U6~A4809E3R-263DN~~FINAL_PART~~.pdf11:56
lekernelneed to check11:56
adamw_our inventory have this part about 3k!11:56
lekerneliirc I had ordered it from Mouser, but that was some 4 years ago11:57
adamw_the delay time is 200ms, N-Channel Open drain11:57
lekerneloh, ok11:57
lekernelperfect then?11:57
adamw_but the threshold voltage is 2.63V11:57
adamw_it should be work well.11:58
lekernelyeah, I think so11:58
adamw_just soldered11:58
adamw_not tested then11:58
adamw_did u use an diode to block/protect?11:58
lekernelthe NOR flash is specified at 2.7V mini11:59
lekernelit should be fine11:59
lekernela diode, where?12:00
lekernelhttp://lekernel.net/blog/wp-content/uploads/2009/01/ula_schematics.pdf12:00
lekernelthat was my max6303 circuit... but with an altera fpga12:00
adamw_i check MAX6303, it's not a open drain. so u must need a diode.12:01
lekernelha12:01
lekernelyes12:01
lekernelbut test the A4809 first :)12:01
adamw_sure.12:02
adamw_cathode of diode is connected to RP#, and the anode of diode is connected to PROGRAM_B on my site12:03
adamw_please don't DO this on your MAX6303.12:03
adamw_I'll report if the result is good.12:04
adamw_wow, the circuit is designed in 2007?!12:05
lekernelyeah12:06
lekernelyour diode connection looks good12:07
lekernelmh, no actually12:07
lekernelyou should do it the other way12:07
lekernelotherwise the FPGA will de-configure itself when pulling RP# low to reset the flash12:07
adamw_any news about reset ic analysis I always updated here: http://en.qi-hardware.com/wiki/Milkymist_One_Power_On_Off_Sequence12:08
lekernelso you should connect the reset IC to PROGRAM_B and put the diode the other way around12:08
adamw_wrong direction of diode?12:09
lekernelalso, this is directly max6303 compatible (no need for open drain), since nothing else drives PROGRAM_B12:09
lekernelyeah, and wrong position of the reset IC if you put it on RP#12:09
adamw_right, nothing drives PROGRAM_B.12:10
adamw_no no..I located reset ic on PROGRAM_B.12:10
adamw_then reset ic's output goes to PROGRAM_B.12:11
lekernelok. then you should connect the cathode of the diode to PROGRAM_B and anode on RP#12:11
lekernelso the diode is conductive when V(PROGRAM_B) < V(RP#)12:11
lekerneli.e. pull RP# low when PROGRAM_B is low12:11
adamw_anode is positive terminal, cathode is negative terminal.12:14
adamw_your connection will let fpga to reconfigure again when whatever RP# pulls low then high(assert RESET condition)12:19
adamw_is that right?12:20
adamw_but my idea is to let RP# pin got low when power up and delay 200ms at low level then high, also when RP# get low from fpga asserting reset.12:23
adamw_so your connection I confused. ;-) I was thought my connection is right since I've not soldered that diode.12:24
adamw_Shall we need to reconfigure fpga (from PROGRAM_B) whenever asserting NOR flash reset? I was thought they are different operation. :-)12:27
lekerneladamw_: no, we shall NOT reconfigure fpga (from PROGRAM_B) whenever asserting NOR flash reset12:27
lekernelso the diode's cathode must connect to PROGRAM_B12:28
lekernelit's an active low signal!12:28
lekernelduring normal operation, PROGRAM_B is at 3.3V12:29
lekerneland RP# can be at either 0V or 3.3V12:29
lekernelwhen it's at 0V we have12:30
lekernelthe diode's cathode (PROGRAM_B) at 3.3V and the diode's anode (RP#) at 0V12:30
lekerneltherefore, the diode is blocked, current does not flow through it, and nothing happens12:30
lekernelwhich is what we want :)12:30
lekernelon the other hand, during reset, we have PROGRAM_B pulled low at 0V by the reset IC, and RP# floating at 3.3V12:31
lekernelthen, the diode has its cathode (PROGRAM_B) at 0V and its anode (RP#) at 3.3V12:31
lekerneltherefore it becomes conductive and pulls RP# low, which is, again, what we want12:32
lekernelis that clear now?12:32
adamw_hmm...you are totally right! I was wrong. hehe..:-)12:37
adamw_so during activation of reset ic, RP# floating until finishing configuration. right?12:39
adamw_right right12:53
lekernelduring the activation of the reset IC, RP# isn't floating, it's pulled low by the diode13:11
adamw_yes, it connected inside fpga is floating, right?13:14
adamw_i think so.13:14
lekernelah, you mean inside the FPGA? yes13:15
adamw_yeah..inside fpga, i think so.13:16
lekernelbefore configuration the FPGA doesn't drive RP#, only with a weak pull-up13:16
lekernelafter configuration it totally depends on the bitstream13:17
lekerneli'll make that pin open drain13:17
adamw_i tried to find if there's some description on those behaviour like (weak pull-up) inside fpga in document, do you know which doc Xilinx describes?13:18
lekernelmaybe spartan 6 user guide... look for information about "hot swapping"13:19
adamw_yeah...remember to let it be as open drain pin after configuration. tks.13:19
adamw_hm..ok13:19
lekerneliirc this behaviour is controlled by the HSWAP_EN pin and it's enabled on the MM113:19
lekernelbut in all cases, the FPGA shouldn't drive pins before configuration13:19
lekernelyou actually see the weak pull up on the LEDs btw13:20
lekernelthey are dimly lit when the FPGA isn't configured13:20
adamw_yeah...yes13:21
adamw_i just also want to know this time slot understood http://en.qi-hardware.com/wiki/File:Configuration_sequence.png13:21
adamw_this sequence if I can know the behaviour behind those sequences then study the electrical behaviour should be good to understand whole process of configuration.13:22
Fallenouyou may find some interesting stuff page 66 of Spartan 6 FPGA Configuration user guide13:28
Fallenouug380.pdf13:28
Fallenouabout some pin states13:29
Fallenouhttp://www.xilinx.com/support/documentation/user_guides/ug380.pdf13:29
adamw_Fallenou, hi yes, just seeing it about HSWAPEN. :-)13:30
Fallenouhi :)13:30
adamw_Fallenou, hmm...page 67 shows Floating signal levels are problematic in CMOS logic systems.13:31
adamw_well...i need to read more carefully on this mention.13:32
lekerneladamw_: yes, that's why there are those pull up resistors13:33
lekernelso the signals aren't floating13:33
lekernelwolfspraul: we can go to the photography studio, but it's in Köln14:05
lekernelI was there last month... bad timing :(14:05
wolfspraulsaw it, on my list. I will try a new studio we found in Shanghai too.14:06
lekernelsaw it? well, I didn't know the location14:08
lekernelbut he just answered this morning14:08
lekernelif I can get a chance i'd like to meet him as well, he shoots interesting places as well (particle accelerators, neutrino detectors and the like)14:09
lekernelif this can wait a bit I'll go there in early May14:10
lekernelhttp://www.eetimes.com/electronics-products/electronic-product-reviews/fpga-pld-products/4209506/LatticeMico8-FPGA-microcontroller-boasts-new-C-compiler15:53
lekernelthough the LM8 licensing is unclear (last time I checked)15:53
lekernelhttp://www.latticesemi.com/products/intellectualproperty/referencedesigns/8bitmicrocontrollermico8.cfm says "The LatticeMico8 is licensed under a new open intellectual property (IP) core license, the first such license offered by any FPGA supplier. The main benefits of using open source IP are greater flexibility, improved portability, and no cost. This new agreement provides all the benefits of standard open source and allows users to15:55
lekernelmix proprietary designs with the open source core."15:55
lekernelthen when you try to download it, you get this: http://www.latticesemi.com/dynamic/view_document.cfm?document_id=3878015:56
lekernelI contacted Lattice a while ago about this, and they said "we will resolve this"... but they didn't15:56
Fallenou=(15:57
lekernelwell, anyway, LM8 wouldn't make a nice LLHDL demo, the code is full of generate statements and old verilog-95 syntax that would be a pain in the ass to implement15:59
larsclekernel: do you see any problems with using LLHDL as a basis for a simulator?16:01
kristianpaullekernel: i tought you already tested llhdl with navre?..16:01
lekernelthere are already good simulators, why yet another one?16:01
kristianpaulagree16:02
larscto learn how to write one16:02
lekernelwell, indeed a LLHDL simulator wouldn't be very hard to write16:03
lekernelbut I was rather thinking of generating back Verilog models of LLHDL code so I could simply use off the shelf tools for this purpose16:03
kristianpaullarsc: very good point ;-)16:04
lekernelwhich also enables me to use formal verification tools that take Verilog as input, in case of difficult to track LLHDL bugs16:04
kristianpauli guess is too soon to ask, but what are/will the main diferences between verilog and llhdl?16:05
lekernelas the name says, LLHDL is lower level16:06
lekernelso you don't have to deal with the complex structures and idiosyncrasies of Verilog/VHDL to manipulate it16:06
lekernellarsc: also, going the "verilog model" way enables mixed simulations to be made16:08
lekernelie simulate the LLHDL model of a part of the code along with the original Verilog of the rest16:08
lekernelthis would also help in tracking down LLHDL toolchain bugs16:08
lekernellarsc: what do you think?16:10
lekernelah, and LLHDL is _only_ for synchronous designs16:11
lekernelfor asynchronous stuff, you have to manually instantiate the clock domain transfer elements at the boundaries16:12
lekernela LLHDL simulator wouldn't handle that, but a Verilog one will...16:12
larschm16:13
lekernelat least, the event driven ones. there are also cycle-driven Verilog simulators, which have the same synchronicity requirement as LLHDL16:13
larscwhat i would like to see is a simulator where you can write modules in non hdl languages, which allow you to model external behavior16:24
lekernelVerilator is probably what you're looking for :)16:26
lekernelcompiles synchronous Verilog a library C++ classes, which you are free to link to anything you want16:27
lekernelit works great16:27
larscnot exactly what i want, but close16:33
lekernela lot of great work has gone into verilator, so I'd rather recommend you find a way to link your other modules to C++ instead of starting from scratch...16:36
lekernelverilator-compiled modules are really fast. beats most verilog simulators, including the ones with big licenses16:37
mwallelekernel: lm32 reference manual, opcode overview table18:42
mwalle100111 and 11010118:42
lekernelmaybe contact Lattice about that... they fixed the problems last time18:42
mwalle(lm8 toolchain) yet another unmaintained toolchain? :=)18:43
mwallelekernel: is the lm8 still restricted to lattice devices?18:49
lekernelyeah18:49
lekernelanyone happens to know how to complement a positive number with gmplib?19:43
lekernelmpz_com() inverts the (implied) sign bit as well, i.e. mpz_com(1) = -219:43
lekernelbut I want 019:44
lekernel@#[~{#[!19:55
lekernelwhy did they make that such a difficult problem19:56
lekernelwell, probably because it's not meant for arbitrary bit vectors but arbitrary integers :p20:13
lekernelworks by xoring the right number of 1's :)20:16
lekernelbtw got the carry chain arithmetic to work... https://github.com/lekernel/llhdl/blob/master/llhdl-spartan6-map/carryarith.c20:17
Action: rjeffries sees some of the usual suspects22:49
rjeffrieswas MM pcb designed using KiCad oe oether s/w>22:51
lekernelhaha, always the good questions :) no, it was designed with proprietary software22:52
rjeffriesI am not here to cause problems it was curiosity question only22:52
rjeffrieswpwrak is using kiCad now on his small Ben add-ons22:53
lekernelyup. but the MM1 PCB is a lot more complex, and we wanted to avoid kicad woes on this one22:53
rjeffriesnot sure what else has been made from KiCad22:53
lekernelin hindsight, this might not have been such a good idea22:53
rjeffriesunderstood.22:53
lekernelaltium made its lot of problems too22:53
rjeffrieshow many layers is your pc? I would guess 6 at least?22:54
lekernelyeah 622:54
rjeffriesis ben a 4 layer PCB I would guess22:54
lekernelI don't know22:54
rjeffriesok22:54
rjeffrieswronh channel ;)22:54
lekernelif there's a successor to the MM1, we'll probably consider kicad for it22:54
rjeffriescool22:55
rjeffriesI can understand why some people are enthusiastic about MM potential.22:55
wpwrakrjeffries: my boards are all 1-2 layer. haven't designed anything i couldn't prototype in-house yet :)22:56
lekernelcool, the llhdl toolchain correctly handles this: https://github.com/lekernel/llhdl/blob/master/designs/blinker/blinker.v22:57
Action: rjeffries nods to w[wrak22:57
lekerneland the design works on the real hardware22:57
rjeffriesdoes MM1 have a microSD slot availble from exterior?22:58
lekernelno, it's only internal memory card22:58
lekernelyou can think of it as a "hard disk"22:58
lekernelmemory card hotplugging is too much software and mechanical trouble for what it brings22:58
rjeffriesif ther e is something beyond MM1 (and I realize that is a big "if") would you consider adding a second 8:10 port to outside as an i/o? still have one internal as memory22:59
lekernelno idea :)22:59
rjeffrieswell as you know wpwrak's stuff are not memory cards. ;)22:59
rjeffrieswould be nice SWEET to leverage all his work23:00
Fallenou http://www.liquidpcb.org/Screenshots/screenshots.html23:05
Fallenouwhat do you think of this ?23:05
Action: wpwrak wonders if a verilog parser could simply accept { and } as begin/end, and thus avoid the faux pascalism23:07
lekernelwpwrak: yeah I think so23:08
lekernelbut then those verilog files couldn't be used with simulators, other tools, etc.23:08
lekernelso it's not that much of a good idea23:08
lekernelbut if you want, you could add a --werner option to llhdl-verilog ;)23:09
lekernelFallenou: interesting, thanks for the link23:10
rjeffriesFallenou your design shows some fresh thinking. how complex a project can it handle currently?23:10
FallenouI never used it23:11
Fallenoubut a colleague just linked it to me23:11
Fallenouwhere I am doing my internship they used that to design their PCBs23:11
rjeffriesmy mistake I thought it was your project23:11
Fallenouno not at all :)23:11
Fallenoujust a link23:11
FallenouI think they did like 4 layers pcb with it23:12
wpwraklekernel: the parser could also have a mode to just spit out "regular" verilog. may be worth a try. i think it could look a lot tidier.23:12
Fallenoupretty well done pcb btw, but a bit big, but it's a prototype23:12
lekernelwpwrak: there are tons of problems with verilog, this one is by far not the most important23:13
wpwraklekernel: heh, you have to start somewhere ;-)23:14
lekernelfor example I'd rather see that one "fixed"23:14
lekernelhttp://lists.milkymist.org/pipermail/devel-milkymist.org/2010-February/000388.html23:14
lekernelunlike begin/end syntax, this one can make you waste days or debugging or even manufacture broken ASICs if you're not very careful23:15
wpwrakbtw, do the numbers in increments/decrements always have to be sized ?23:15
lekernelin general it's good coding practice yes23:17
lekernelas I said, integer constants default to 32 bits23:17
wpwrakso the synthesizer is not (generally) expected to simplify this. pity. looks like a lot of redundancy. e.g., if you resize the register, then you also have to track down all of the operations on it. or would you get an error/warning if using a smaller/larger value ?23:21
lekernelactually, modern synthesizers do simplify this23:24
lekernelFallenou: http://anthonix.resnet.scms.waikato.ac.nz/toporouter/23:25
wpwrak(000388.html) hmm, subtle. there's a "not" missing in the explanation, no ? e.g., ''the scheduling of the "assign o=r_o" [...] may [not?] occur before you read o again''23:27
wpwrak(toporouter) mmh. an autorouter. isn't the common wisdom that they usually don't work ? :)23:29
Fallenouwo nice lekernel :)23:31
FallenouI always found autorouters sucked23:31
wpwrakthe context-sensitive menus in liquidpcb look interesting. that's a big nuisance in kicad. e.g., if you delete a track, and you click at/near a node, then you have to choose which of the segments you want to select. then, of course, "delete track" deletes all the segments of that track ...23:34
wpwrak(well, maybe it's better in the latest version. i'm a bit behind.)23:35
Fallenouyes that's a pain in the ass23:35
Fallenoubut i havn't touch kicad for more than one year23:36
mwallegn823:42
lekernel'n823:44
Fallenougn823:45
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