kmj | yo | 01:25 |
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kmj | Anyone happen to know about using the HPDMC in a SDRAM (non-ddr) environment on a smaller fpga like Cyclone III or Spartan-3e? | 01:27 |
lekernel | kmj: yeah, it's used with sdr on cyclone2 in the zet86 project | 04:01 |
aeris | adamw_ *\o/* | 04:46 |
adamw_ | aeris, hi | 04:54 |
CIA-45 | flickernoise: Sebastien Bourdeauducq master * re7d1b14 / patches/Lekernel - Eerie Beri.fnp : New patch (for video in) - http://bit.ly/gaiY68 | 09:40 |
kmj | lekernel: I've downloaded zet with the modified hpdmc. I've got it to synthesize, but I still have to figure out to drive the darn thing. | 11:11 |
lekernel | who wants to go to London? | 16:25 |
kristianpaul | seems not you ;-) | 16:27 |
kristianpaul | oh, i see (mail) | 16:34 |
lekernel | i'm going next week... bad schedule :( | 16:34 |
kristianpaul | Fallenou: telnet (milkymist_networking), dint worked for me, and i dint tried on qemu as i have a M1 bord with me | 16:39 |
kristianpaul | Fallenou: anyway, i'll it again and document my results including a pcap capture | 16:39 |
kristianpaul | i'll do it* | 16:40 |
kmj | anyone else want to pull their hair out dealing with dram memory controllers? | 17:37 |
kmj | or is it just me? :) | 17:38 |
lekernel | from what i've heard, it's a recurrent problem in most fpga hobbyist and even industrial projects :) | 18:04 |
lekernel | i've had my share of issues with it as well... | 18:04 |
lekernel | but it's also a very instructive thing to do. actually, it makes it easier to judge the technical quality of projects by looking at whether they got the DRAM to work or not... | 18:06 |
lekernel | since opencores contains hundreds of pieces of worthless crap, you need fast criteria like this :) | 18:09 |
kmj | lekernel: hahaha | 19:54 |
kmj | lk: it is a recurrent problem. I first tried with Xilinx, using their Memory Interface Generator(MIG) where they auto-generate a memory controller. | 19:54 |
kmj | Their controller is approximately 7300 lines of code. | 19:55 |
kmj | While I think the idea of "opencores" is a great one --- in all practicality, most don't work ----or likely don't work on the hardware you have. | 19:55 |
kmj | The auto-generating memory controller is a pretty awesome concept. They claim to have verified every possible output. | 19:56 |
kmj | Even USING pre-made controllers is hard. | 19:57 |
kmj | After screwing around for a couple hours, I (think) I've managed to get zet's version of the hpdmc to initialize some memory, I think. | 19:59 |
lekernel | use a simulator... | 19:59 |
kmj | but of course since I haven't written a read/write state machine(s) yet, I can't know. There's no real "INIT_DONE" signal sent back from the memory | 19:59 |
lekernel | yup. that's what the "hard" in "hardware" stands for. | 20:00 |
kmj | lek: That's a possibility. Assuming that I have an HDL implementation for a DRAM chip that is reliable. | 20:00 |
lekernel | micron provides good verilog models for their chips | 20:00 |
kmj | zet included a memory chip, but I haven't checked the data sheet to see if its the same | 20:01 |
kmj | lek: that's pretty neat that they do that. I guess I'm surprised. I would think it would have to be pretty reliable | 20:01 |
lekernel | SDRAMs are all very similar... there are JEDEC standards for them | 20:01 |
kmj | Isn't the JEDEC just physical and maybe protection from ESD, etc? | 20:01 |
lekernel | if you use hpdmc and get the timings, the geometry and the initialization sequence right, it should work with your other chip | 20:02 |
kmj | Assuming the width, number of banks, performance etc is the same | 20:02 |
kmj | but that's big assumptions | 20:03 |
lekernel | you probably have to change that | 20:03 |
kmj | That seems like a big change to me. but I'm new to this. | 20:03 |
kmj | I've got some working FPGA projects | 20:03 |
kmj | so I know enough to hurt myself | 20:03 |
lekernel | actually don't even try without checking first, because there's a high probability they aren't the same, and it won't work if there's a problem there | 20:03 |
kmj | right | 20:04 |
lekernel | or worse, you'll get aliased memory addresses and other niceties | 20:04 |
lekernel | which can give you a lot of debugging pain when your system doesn't work because the data in DRAM is corrupted | 20:05 |
kmj | Sure. | 20:05 |
kmj | In comparison to on-chip resources like m9k from altera or block rams from xilinx, DRAM is ridicuously more complicated. | 20:06 |
kmj | SRAM is nice but expensive and not enough to go around | 20:06 |
kmj | I used some serial memory, and that is nice, but same issues as SRAM | 20:07 |
kmj | I was checking out tmplab earlier | 20:08 |
lekernel | yeah, DRAM is difficult, but there's no way around, so bite the bullet :) | 20:08 |
kmj | haha. I've tried and given up on DRAM a few times | 20:09 |
kmj | I want to make small scan-converter | 20:09 |
lekernel | there's the PSRAM (pseudo-SRAM) but only if you don't need performance (it's slow as hell) and it's also quite expensive (but still cheaper than SRAM) | 20:09 |
kmj | I saw that PSRAM out on digi-key's site but I haven't read into it. | 20:10 |
lekernel | PSRAM is DRAM with an integrated controller that exposes an SRAM-like interface (and always takes the worst case timings for the internal DRAM core, hence the poor performance) | 20:10 |
kmj | Shopping from RAM is a PITA | 20:10 |
lekernel | well, you might not want PSRAM for a high bandwidth application like a scan converter | 20:10 |
kmj | Poor performance like 75mhz or something, or poor like 15mhz? :) | 20:11 |
lekernel | so get some SDRAM :) | 20:11 |
lekernel | iirc it is about 30MHz | 20:11 |
kmj | Yah. I'm doing something pretty low-res | 20:11 |
kmj | 320x200x12-bits to 640x400x12. But the output is still I think, a 25mhz pixel clock | 20:12 |
lekernel | but do you really want to pay extra for special and expensive PSRAM chip when a cheap and readily available PC133 SDRAM chip could do the same job with a bit more work on the fpga design? | 20:12 |
kmj | Well, the other thing is this: DRAM is commonly on these eval boards. I can't go interfacing other big (parallel) chips or I eat all the spare I/O on them. | 20:13 |
kmj | It's a little diff when you are designing your own PCB, project, etc where you can pick and choose what parts you need | 20:13 |
kmj | I need a decent working DRAM controller that gives you a sram-like interface. Is that too much to ask? :) | 20:14 |
lekernel | yeah, because it's physically impossible unless you can accept poor performance | 20:18 |
lekernel | (or very high cost) | 20:20 |
kmj | Right. As soon as you go to serial, etc, your peformance goes in the toilet unless you run crazy frequency busses | 20:20 |
kmj | It's funny that with sata, SAS, USB 3.0, you've got a move back to serial | 20:20 |
lekernel | FPGA's with GHz-capable I/Os aren't uncommon those days | 20:20 |
kmj | They are for the hobbyist. For my pocketbook. | 20:20 |
kmj | Forget about Stratix and Virtex | 20:20 |
lekernel | oh, not at all | 20:20 |
kmj | which? | 20:20 |
lekernel | spartan 6 can have 1 GHz I/Os when you use the serializers | 20:20 |
kmj | Do they have built in MGTs? | 20:20 |
lekernel | some have something like that | 20:21 |
lekernel | and all have SERDES that reach ~1Gbps/pin | 20:21 |
kmj | Well, ok, I found a spartan-6 board for $250. I guess that's not too bad | 20:22 |
kmj | but you know these high-frequency designs are exactly easy | 20:22 |
kmj | s/are/aren't | 20:22 |
--- Tue Jan 25 2011 | 00:00 |
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