#milkymist IRC log for Monday, 2011-01-24

kmjyo01:25
kmjAnyone happen to know about using the HPDMC in a SDRAM (non-ddr) environment on a smaller fpga like Cyclone III or Spartan-3e?01:27
lekernelkmj: yeah, it's used with sdr on cyclone2 in the zet86 project04:01
aerisadamw_ *\o/*04:46
adamw_aeris, hi04:54
CIA-45flickernoise: Sebastien Bourdeauducq master * re7d1b14 / patches/Lekernel - Eerie Beri.fnp : New patch (for video in) - http://bit.ly/gaiY6809:40
kmjlekernel: I've downloaded zet with the modified hpdmc. I've got it to synthesize, but I still have to figure out to drive the darn thing.11:11
lekernelwho wants to go to London?16:25
kristianpaulseems not you ;-)16:27
kristianpauloh, i see (mail)16:34
lekerneli'm going next week... bad schedule :(16:34
kristianpaulFallenou: telnet (milkymist_networking), dint worked for me, and i dint tried on qemu as i have a M1 bord with me16:39
kristianpaulFallenou: anyway, i'll it again and document my results including a pcap capture16:39
kristianpauli'll do it*16:40
kmjanyone else want to pull their hair out dealing with dram memory controllers?17:37
kmjor is it just me? :)17:38
lekernelfrom what i've heard, it's a recurrent problem in most fpga hobbyist and even industrial projects :)18:04
lekerneli've had my share of issues with it as well...18:04
lekernelbut it's also a very instructive thing to do. actually, it makes it easier to judge the technical quality of projects by looking at whether they got the DRAM to work or not...18:06
lekernelsince opencores contains hundreds of pieces of worthless crap, you need fast criteria like this :)18:09
kmjlekernel: hahaha19:54
kmjlk: it is a recurrent problem.  I first tried with Xilinx, using their Memory Interface Generator(MIG) where they auto-generate a memory controller.19:54
kmjTheir controller is approximately 7300 lines of code.19:55
kmjWhile I think the idea of "opencores" is a great one --- in all practicality, most don't work ----or likely don't work on the hardware you have.19:55
kmjThe auto-generating memory controller is a pretty awesome concept. They claim to have verified every possible output.19:56
kmjEven USING pre-made controllers is hard.19:57
kmjAfter screwing around for a couple hours, I (think) I've managed to get zet's version of the hpdmc to initialize some memory, I think.19:59
lekerneluse a simulator...19:59
kmjbut of course since I haven't written a read/write state machine(s) yet, I can't know. There's no real "INIT_DONE" signal sent back from the memory19:59
lekernelyup. that's what the "hard" in "hardware" stands for.20:00
kmjlek: That's a possibility.  Assuming that I have an HDL implementation for a DRAM chip that is reliable.20:00
lekernelmicron provides good verilog models for their chips20:00
kmjzet included a memory chip, but I haven't checked the data sheet to see if its the same20:01
kmjlek: that's pretty neat that they do that. I guess I'm surprised. I would think it would have to be pretty reliable20:01
lekernelSDRAMs are all very similar... there are JEDEC standards for them20:01
kmjIsn't the JEDEC just physical and maybe protection from ESD, etc?20:01
lekernelif you use hpdmc and get the timings, the geometry and the initialization sequence right, it should work with your other chip20:02
kmjAssuming the width, number of banks, performance etc is the same20:02
kmjbut that's big assumptions20:03
lekernelyou probably have to change that20:03
kmjThat seems like a big change to me. but I'm new to this.20:03
kmjI've got some working FPGA projects20:03
kmjso I know enough to hurt myself20:03
lekernelactually don't even try without checking first, because there's a high probability they aren't the same, and it won't work if there's a problem there20:03
kmjright20:04
lekernelor worse, you'll get aliased memory addresses and other niceties20:04
lekernelwhich can give you a lot of debugging pain when your system doesn't work because the data in DRAM is corrupted20:05
kmjSure.20:05
kmjIn comparison to on-chip resources like m9k from altera or block rams from xilinx, DRAM is ridicuously more complicated.20:06
kmjSRAM is nice but expensive and not enough to go around20:06
kmjI used some serial memory, and that is nice, but same issues as SRAM20:07
kmjI was checking out tmplab earlier20:08
lekernelyeah, DRAM is difficult, but there's no way around, so bite the bullet :)20:08
kmjhaha. I've tried and given up on DRAM a few times20:09
kmjI want to make small scan-converter20:09
lekernelthere's the PSRAM (pseudo-SRAM) but only if you don't need performance (it's slow as hell) and it's also quite expensive (but still cheaper than SRAM)20:09
kmjI saw that PSRAM out on digi-key's site but I haven't read into it.20:10
lekernelPSRAM is DRAM with an integrated controller that exposes an SRAM-like interface (and always takes the worst case timings for the internal DRAM core, hence the poor performance)20:10
kmjShopping from RAM is a PITA20:10
lekernelwell, you might not want PSRAM for a high bandwidth application like a scan converter20:10
kmjPoor performance like 75mhz or something, or poor like 15mhz? :)20:11
lekernelso get some SDRAM :)20:11
lekerneliirc it is about 30MHz20:11
kmjYah. I'm doing something pretty low-res20:11
kmj320x200x12-bits to 640x400x12. But the output is still I think, a 25mhz pixel clock20:12
lekernelbut do you really want to pay extra for special and expensive PSRAM chip when a cheap and readily available PC133 SDRAM chip could do the same job with a bit more work on the fpga design?20:12
kmjWell, the other thing is this: DRAM is commonly on these eval boards.  I can't go interfacing other big (parallel) chips or I eat all the spare I/O on them.20:13
kmjIt's a little diff when you are designing your own PCB, project, etc where you can pick and choose what parts you need20:13
kmjI need a decent working DRAM controller that gives you a sram-like interface. Is that too much to ask? :)20:14
lekernelyeah, because it's physically impossible unless you can accept poor performance20:18
lekernel(or very high cost)20:20
kmjRight. As soon as you go to serial, etc, your peformance goes in the toilet unless you run crazy frequency busses20:20
kmjIt's funny that with sata, SAS, USB 3.0, you've got a move back to serial20:20
lekernelFPGA's with GHz-capable I/Os aren't uncommon those days20:20
kmjThey are for the hobbyist. For my pocketbook.20:20
kmjForget about Stratix and Virtex20:20
lekerneloh, not at all20:20
kmjwhich?20:20
lekernelspartan 6 can have 1 GHz I/Os when you use the serializers20:20
kmjDo they have built in MGTs?20:20
lekernelsome have something like that20:21
lekerneland all have SERDES that reach ~1Gbps/pin20:21
kmjWell, ok, I found a spartan-6 board for $250. I guess that's not too bad20:22
kmjbut you know these high-frequency designs are exactly easy20:22
kmjs/are/aren't20:22
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