#qi-hardware IRC log for Wednesday, 2017-06-28

promachDocScrutinizer05: I need to find out why the book needs to use Figure b10:01
promachFor UART, if Tx device transmits at 9600Hz, Rx device need to sample at sampling frequency of at least twice that of 9600Hz ?10:03
DocScrutinizer05more like 16*10:05
DocScrutinizer05the circuit in the book lacks a DC-blocker cap and 3* R for biasing input. They simplified and messed it up due to too much simplification10:07
DocScrutinizer052*R at least10:08
promachhuh ? 2*R ? where ?10:11
promachfor UART Rx, what's the benefit of sampling more often?11:29
DocScrutinizer05detecting edges, so you know more precisely where's *middle* of a bit time window11:45
DocScrutinizer05UART waits for leading edge of startbit, then samples all data bits at middle of the bit period. since the clock for the hw isn't async, it needs an as finfrained as possible oversampling to detect *leading* edge of startbit to map it to internal clock 11:47
DocScrutinizer052*R at input to bias 11:47
DocScrutinizer05alas that would also attenuate the input signal, or at least change input impedance, so they ommitted it11:49
DocScrutinizer05for an analog amp you want all transistors (except in complementary bridges, and even there depending on whether it's more of a class A or AB or class B) to draw some quiescent current11:54
DocScrutinizer05tying input gate to GND doesn't make sense in that circuit in your book11:54
DocScrutinizer05the amp is in extreme clipping situation11:55
DocScrutinizer05re UART I wasn't as clear as I should. The clock needs to be 8 or 16 times higher than bitrate. So the leading edge of startbit can get determined to a 1/8 or 1/16 of bit-time precision. Then (for 16 times oversampling) the hardware samples all subsequent data bits at $time_of_startbit_edge + N(bit)*16 + 812:03
DocScrutinizer05the "jitter" you have is bitrate/16 then, since the clock won't phaseshift on detecting startbit leading edge12:04
DocScrutinizer05*if* you had a clock oscillator you could stop, and then start it on detecting leading edge of startbit, then a oscillator clock frequency of bitrate*2 would suffice12:05
DocScrutinizer05then you,d sample first bit on clock period#3, 2nd bit on #5, 3rd on #7 a s o12:06
DocScrutinizer05since you use an exernal clock, you want oversampling to approximate that ideal behavior12:07
DocScrutinizer05it's all about the precision of your detecting the startbit leading edge12:10
promachgive me a moment on UART.12:10
DocScrutinizer05not exactly to the point, but related12:13
promachDocScrutinizer05: Why (for 16 times oversampling) the hardware samples all subsequent data bits at $time_of_startbit_edge + N(bit)*16 + 812:18
DocScrutinizer05your (external) clock and the serial data bitrate 'clock' interfere aka "alias" with each other, since the external clock isn't synced to the bitrate. so with a clock frequency of bitrate * 2 your databit sampling could happen *anywhere' within the bit period, from leading edge to trailing edge. With 4 times oversampling it will happen anywhere from 25% to 75% of bit period, so a lot closer to the center already12:18
promachWhy With 4 times oversampling it will happen anywhere from 25% to 75% of bit period ?12:22
DocScrutinizer05first sampling point detects startbit level. now you add 1 bitperiods and sample again. When will this sample happen? Answer: anywhere between startbit-leading-edge+0 + 1_bit_period, and startbit+startbitduration + 1_bit_period12:23
DocScrutinizer05Why With 4 times oversampling it will happen anywhere from 25% to 75% of bit period ? ::: because then the startbit leading edge gets detected with a precision of bitperiod/412:24
DocScrutinizer05you don't know when the startbit leading edge happens since the UART only **samples** to detect the edge12:25
DocScrutinizer05you only know with a precision of the sample period12:25
DocScrutinizer05it's not edge triggered12:25
DocScrutinizer05it's sort of like Heissenberg12:29
promach startbit+startbitduration + 1_bit_period   .....   75% ?12:30
promachhow do you get 75% for 4 times oversampling ?12:30
DocScrutinizer050% to 25%, 25% to 50%, 50% to 75%, and 75% to 100%. So your precision is +/- 25%, aka from 25% to 75%12:32
promachI do not understand ?12:32
promachwhat about  startbit+startbitduration + 1_bit_period ?12:32
DocScrutinizer05and you got an 'error margin' of 25% to both leading and trailing edge12:32
DocScrutinizer05sorry, I give up, I'm not up to the task of explaining this12:33
promachnever mind. I found that to obtain Rout, Vin has to be shorted to ground12:33
promachwhich is Figure b12:33
DocScrutinizer05that's gibberish12:34
DocScrutinizer05I don't know who came up with this12:37
DocScrutinizer05it's faintly correct for *real* working circuits, but figure b is no working circuit, it's defect by design since it has no bias12:38
DocScrutinizer05and no DC decoupling to protect the bias12:38
promachFigure b is a test circuit to measure Rout12:39
DocScrutinizer05sorry, I got other stuff to do12:39
DocScrutinizer05you can't measure the Rout of a broken circuit12:39
DocScrutinizer05it's meaningless12:40
DocScrutinizer05the circuit is meant for an input voltage swing of maybe GND+0.7V to VDD-<whatever>. Outside of that voltage range the circuit doesn't work, so it's bullshit to probe for any properties of the circuit when grounding input12:42
DocScrutinizer05sorry I have to say that, but that except of the suggests the book is wrong regarding that. I can't rule out the rest of the book provides context that redefines the situation12:45
DocScrutinizer05of the book12:45
DocScrutinizer05so what? doesn't apply to circuits operated outside their operational range12:48
DocScrutinizer05"zero" means "with respect to the allowed input voltage swing, which is +/-x Volt around zero"12:49
DocScrutinizer05for your circuit 0 volt isn't the middle of the allowed voltage swing, it isn't even inside allowed voltage swing at all12:50
DocScrutinizer05somebody ommitted bias, as I said a dozen times already12:51
DocScrutinizer05that circuit is broken from oversimplification12:51
DocScrutinizer05depending on particular type of MOSFET used in input stage12:52
DocScrutinizer05the usual mosfet will close completely when gate is on source level12:52
DocScrutinizer05so that transistor isn't operating in its linear range which is a BAD THING for a linear amp12:53
DocScrutinizer05not in linear rnage means the transistor can't close even more when you apply a negative voltage with respect to GND to the input. Usually that is called CLIPPING12:54
DocScrutinizer05clipping is something you need to avoid by all means for a linear amp12:55
promachDocScrutinizer05: that test circuit is for small-signal analysis of Rout12:56
DocScrutinizer05WTF, you build a circuit that is made to test some property of that circuit? what's its true useage12:57
DocScrutinizer05small signal HAHA. There is no signal small enough to bring that test circuit in b) out of clipping12:57
DocScrutinizer05so forget it12:57
DocScrutinizer05tis IS NO amp12:58
DocScrutinizer05it starts to become an amp when you apply at least 0.7V bias with respect to GND12:58
DocScrutinizer05go take it elsewhere12:59
promachthis is small-signal analysis, not DC analysis12:59
DocScrutinizer05google clipping13:00
DocScrutinizer05then google DC-bias maybe13:00
DocScrutinizer05my ass13:01
DocScrutinizer05what you get in fig b) is Rout of an amp **IN CLIPPING MODE**. Everybody can tell you an amp in clipping doesn'T work as amp anymore13:02
DocScrutinizer05it's saturated, clipping, outside of specs, not functional13:03
DocScrutinizer05not my fault you forgot DC-bias of input gate and DC-blocker capacitor13:04
DocScrutinizer05go test your thing in a simulator, you will notice it has a gain of -infinite13:05
DocScrutinizer05unless you apply a bia of at least 0.7 V (or whatever t´is that particular MOSFETs gate voltage where it starts to open D-S channel)13:05
promachI know you are concerned about DC analysis, but simulator also has AC analysis, right ?13:07
DocScrutinizer05ZERO means AC-zero, NOT DC-zero13:07
promachit definitely has, otherwise, we will not have gain-phase plot13:07
promachbode plot13:07
DocScrutinizer05what the fuck is so hard to understand in "fig b) doesn't show an amp"?13:08
promachI understand that  "fig b) doesn't show an amp"?13:08
DocScrutinizer05no fucking DC-analysis, ITS BROKEN BY DESIGN13:08
promachit is not meant for DC analysis13:08
DocScrutinizer05so why do you drive it DC then??????13:08
DocScrutinizer05tying gate to GND **IS DC**13:09
promachVin is not driven by DC anymore13:09
promachafter shorting to GND13:09
DocScrutinizer05apply two resistors for bias, and a DC-blocker capacitor and you are fine13:09
Action: DocScrutinizer05 headdesks13:09
promachin AC analysis, DC bias is deemed GND13:09
DocScrutinizer05please take it elsewhere13:10
DocScrutinizer05your refusal to accept the simple fact that this circuit is broken by design starts to annoy13:10
promachit is broken in DC analysis13:11
promachnot in AC analysis13:11
DocScrutinizer05initally you seem to have spotted the problem yourself when you asked why the feedback isn't working. It's not working BECAUSE the circuit is operated outside specs since it's missing bias and DC-blocking on input13:12
DocScrutinizer05fuck, you really are annoying13:12
DocScrutinizer05its broken. as linear amp. period. 13:13
DocScrutinizer05no matter which analysis you run against it13:13
promachI just understand about AC analysis just now13:13
DocScrutinizer05do you understand about electronics too?13:15
DocScrutinizer05or _just_ about analysis13:15
DocScrutinizer05when this is about education at university then I have little hope for good circuits in the future13:17
DocScrutinizer05>>in AC analysis, DC bias is deemed GND<< yes, OUTSIDE your blackbox DUT13:19
DocScrutinizer05your blackbox however is missing INTERNAL bias13:19
DocScrutinizer05what makes you think your circuit can get away without the DC-blocker capacitor and internal input bias EVERY OTHER circuit has?13:21
DocScrutinizer05s/circuit/non-differential amp/13:21
DocScrutinizer05s/circuit/non-differential amp/g13:22
kyakDocScrutinizer05: fear not - younger generations are always better than older despite older thinking otherwise :)13:22
DocScrutinizer05I see13:22
DocScrutinizer05google "operation point"13:23
DocScrutinizer05secod hit is "bias"13:23
DocScrutinizer05https://en.wikipedia.org/wiki/Operating_point  https://en.wikipedia.org/wiki/Biasing13:24
DocScrutinizer05>>For low distortion, the transistor must be biased so the output signal swing does not drive the transistor into a region of extremely nonlinear operation.<< tying gate to source puts the mosfet into a mode as extremely nonlinear as it gets: it's closed13:26
DocScrutinizer05>>the MOSFET must stay in the active mode (or saturation mode), and avoid cut-off or ohmic operation (or triode mode).<<13:27
DocScrutinizer05ETX, bye13:28
DocScrutinizer05listen buddy, when you're doing AC-analysis the you tie input to GND via a DC-blocker capacitor. You MUST NOT apply DC-bias in the form of tying input to GND with a wire13:44
DocScrutinizer05however you're doing exactly that and then you call it AC-analysis13:45
DocScrutinizer05get your educational books fixed!13:47
DocScrutinizer05when you actually do tie input to GND via a DC-blocker capacitor, you will notice your circuit is junk since it has no input bias circuit defining the operation point of the input stage transistor. The gate is floating13:48
DocScrutinizer05operating point*13:49
DocScrutinizer05your initial question was extremely cute. You found that Rout should differ in *normal operation* from what been calculated by the small signal AC analysis method in https://electronics.stackexchange.com/questions/242397/why-should-we-set-input-source-equal-zero-for-calculating-output-resistance-of-c, due to feedback not working when circuit is not at operation point. Now you just need to stand your thesis and argue why that's 14:00
DocScrutinizer05probably a bad thing14:00
DocScrutinizer05sure you can test Rout at clipping mode, the question is if that's really what you want to know14:02
enycoo fun14:19
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