#qi-hardware IRC log for Thursday, 2017-06-01

strawberyargon!hot10:49
kyak!now11:01
kyaki mean, !not11:01
promachFor UART, how to notify RX that TX has buffer underrun which means the received data is not valid until TX solves buffer underrun issue ?13:13
wpwrakpromach: in a uart, rx and tx are largely independent. one can be idle while the other is working, and if both are busy at the same time, they may be at different bits.13:15
wpwrakpromach: what they typically share is the clock divider for the bit rate and some control registers. but that's all.13:16
promachI do not think they share control registers13:17
promachwpwrak: let's sa it is between two platforms13:17
promachsay*13:17
wpwraki mean on the same device13:18
promachok13:18
promachone more thing13:18
promachFor http://www.ti.com/lit/ds/symlink/pc16550d.pdf#page=17 , how is the output of baud_generator (16x baud) used in transmitter logic ? I only see there is a transmitter timing control block in the functional block diagram, but I am not sure how it works exactly. Anyone ?13:18
wpwraki see you means tx and rx on both ends. there, you don't need to tell rx anything about tx underruns, since each byte has a start bit that synchronizes the receiver13:19
promachwhat is the purpose of generating 16x baud ?13:20
promachI thought 16x baud is used to oversample RX data ?13:21
promachwpwrak13:22
DocScrutinizer05promach: the UART hardware for example does sampling in middle of the bit timing window, and for TX it uses the 16x clock for internal stuff like FIFO register2register transfers etc19:13
DocScrutinizer05on T1 the sending register enabled data output, on T2 the receiving register samples&holds data from the bus. Stuff like that19:14
DocScrutinizer05sending and receiving registers are local and internal here, like two registers of a FIFO19:16
DocScrutinizer05T0: R(N)-out; T1: R(N-1)-strobe; 19:18
DocScrutinizer05http://www.ti.com/lit/ds/symlink/pc16550d.pdf#10  >> tIRS  Delay from Initial INTR Reset to Transmit Start:  8 to 24 BAUDOUT Cycles<<19:27
DocScrutinizer05also see "Figure 3. BAUDOUT Timing"19:29
DocScrutinizer05ff19:30
--- Fri Jun 2 201700:00

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