#qi-hardware IRC log for Tuesday, 2017-01-03

erichvk__wpwrak, did the email and code make it through the usual spam filters?09:55
erichvk__if not, I can stick them onto some ftp space09:56
wpwrakerichvk__:yes, thanks ! just haven't gotten around to processing it yet12:18
erichvk__wpwrak, if you are able to suggest any repositories of example files in the meantime, I can do a bit more testing12:41
wpwrakthere's a lot of stuff in http://projects.qi-hardware.com/index.php/p/kicad-libs/13:08
erichvk__perfect, thanks. I will test a bit more.13:10
erichvk__wpwrak, geda.c, line 9113:38
erichvk__        fprintf(file, "%d %d ", center.x, -center.y);13:38
erichvk__        fprintf(file, "%d %d ", center.x, center.y);13:39
erichvk__seems to be behaving with that one final tweak13:41
erichvk__incidentally, the gEDA PCB fork, pcb-rnd, now can import and export kicad format layouts, and also export .mod files of gEDA footprints in a layout.13:43
wpwrakerichvk__: now checking your mail ... did you get to test the different hole types ? there's some more fun stuff in fped: you can change pad types to make them affect different layers. e.g., normally you have copper + solder mask opening + solder paste. but you can also have pads with just a subset of these14:05
wpwrake.g., look at qfn.fpd: there, you the center pad has no solder paste. instead, it has little sub-pads on it which only provider solder paste14:06
erichvk__geda pcb only has pins or pads. Pins go through all layers, and I have used default mask and copper clearances. Solder paste is not specified in the footprint.14:06
erichvk__gEDA lets you shrink or grow clearance on a per pad/pin basis14:06
erichvk__and same for mask14:07
wpwrakhmm, how do you do qfns then ? for best performance, they want little solder paste islands, not just one big area14:07
erichvk__gEDA generates a solder mask based on the pad settings, but fabs will often do their own thing with the gerbers14:08
wpwraki discussed those pads here: http://lists.en.qi-hardware.com/pipermail/discussion/2011-March/007639.html14:08
erichvk__by solder paste I mean stnecil14:08
wpwrakespecially the NXP document in [1] is an interesting read14:09
wpwrakpoot pcb houses. you make them work hard ;-)14:09
wpwrakpooR, even14:09
erichvk__in gEDA, to achieve the four apperture pad you depict, we'd probably have to merge four pads each with their own solder mask settings 14:10
erichvk__the pcb-rnd fork has a new file format in devellopment which is much more flexible14:11
erichvk__my main goal is to get exported geometry of pins, pads, silk working, accepting that things like solder mask, paste, and (x,y) offset holes in pads and slots will not map easily to gEDA14:12
wpwrak(multiple pads) hmm, if you can make the solder mask off-center, then that would work. else, you could try to approximate. 14:13
erichvk__four pads in a grid, with marginal overlap, and shrunken paste apertures would provide the effect shown14:14
wpwrakokay, that could work. or add little copper-only filler pads14:14
wpwrakfor very "unbalanced" pads, the QFN48 in qfn.fpd are a good example14:15
wpwrakalso, there we're at 9 pads for the large center pad14:16
wpwrakin qfn.fpd i used the variables zone_ratio_35 and paste_ratio_20 to calculate the occupation ratios NXP recommend. so it's easy to check how close the design is to that.14:17
wpwrakadmittedly, an oddball use of variables ;-)14:17
wpwrakerichvk__: do you work with git ? if you commit your changes in a branch, you could make nice patches from that14:18
erichvk__I never got the sign up email14:19
erichvk__not very capable with git branches14:19
wpwrakalso, please don't mix 4 spaces indentation with tab indentation for major levels. major levels are #levels * 1 tab, wrapped lines get an extra four spaces14:20
erichvk__sorry, my bad14:20
wpwrak(mail) hmm, could be part of the mail troubles at the qi-hw server14:20
erichvk__vi pastes spaces instead of tabs, it seems14:21
wpwraki tried to post something to the qi-hw mailing list on the 24th, but it never made it. says "Temporary local problem". alas, wolfspraul doesn't seem to be around these days14:21
wpwraki sent a "ping" to the list today, but that still gets the "Temporary local problem"14:22
wpwrakfortunately, the git repo still works :)14:22
wpwrakbtw, here is a catalog of "pretty-printed" footprints: http://downloads.qi-hardware.com/people/werner/tmp/kicad-libs-modules.pdf14:24
wpwrakmay be useful for finding "interesting" cases with unusual pad configurations and such14:25
erichvk__yeah, p337, qfn 4814:27
erichvk__OK, well that's given me something to think about. For now, hole geometry, sillk, arc line and circle and pad geometry are what 99.9% of gEDA users would be happy with.14:28
erichvk__we will think about how to support the windowing of stencils and solder masks with the new pcb-rnd format14:29
wpwrakfor now, maybe fprintf a warning of if the geda dumper gets a layer mix it doesn't know how to handle ?14:40
erichvk__I'm really only familiar with the individual feature export code; is the dump code different?14:41
erichvk__there's nothing wrong with preserving the design intent in the fpd14:42
erichvk__even if not supported by gEDA14:42
erichvk__comments in footprints start with # and are ignored14:43
erichvk__a simple fprintf starting with a # would do the job in the exported footprint14:43
wpwrakyes, i mean what's in geda.c. and i was thinking of fprintf(stderr, ... :) but putting it into the footprint could also be nice, in case you have things further down the pipeline that may want to know14:46
erichvk__I think most gEDA users will be delighted if I announce fairly complete support and link to your hardware library. They won;t be fussed about minor things like paste/mask stuff.14:48
erichvk__and offset holes in pads/pins15:07
erichvk__the mapping is neither surjective nor injective15:07
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