#qi-hardware IRC log for Sunday, 2015-09-20

whitequarkha, using verilog to go straight to layout, skipping schematic capture02:06
whitequarkI like this: https://twitter.com/azonenberg/status/645412545637969920 http://redmine.drawersteak.com/projects/achd-soc/repository/entry/trunk/boards/hdl-components/power/LTC3374.v02:06
DocScrutinizer05errr, ohwell02:43
DocScrutinizer05I prefer drawing schematics to writing code for generating netlists02:49
whitequarkwriting code would save you so much repeated work02:52
whitequarkyou can support typical design for an entire family of parts with the same code02:53
whitequarkno more forgetting to update something, no more diffs of XML garbage, etc02:53
DocScrutinizer05hmm?03:31
DocScrutinizer05I hardly ever do repeated work03:32
DocScrutinizer05there's a thing called c&p, in e.g. eagle-7 there are even modules that can be as complex as you want and nested arbitrarily deep, and you use them like a chip or any other component in any level of the module hierarchy03:33
DocScrutinizer05and I think odds are I forget something in a verilog "net plan" while in a schematics it's pretty obvious when some wire is missing03:34
DocScrutinizer05prolly a matter of personal preferences03:50
larscnot bad10:11
kristianpaulnot bad indeed15:39
qwebirc15330Hello20:07
qwebirc15330My god ram is a complicated world20:08
qwebirc15330I just figured out that most of ram I bought in the past are 100% crap, overclocked above specs by manufacturer20:08
qwebirc15330Both from G-Skill and Kingston20:09
qwebirc15330I didn't even knew this was a thing20:09
wpwraki guess the ability of combining graphical and textual circuit descriptions would be nice. there are many things where a drawing is much clearer than any "program" would be. but then there are also cases where doing things graphically is just unnecessary torture.23:00
--- Mon Sep 21 201500:00

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