#qi-hardware IRC log for Wednesday, 2015-05-27

arossdotmegot any photo of china factorys that could be used in something say like a info graphic? from a real life photo to a simple,basic - ie: 2 colour outline,silo-wet(cant spell the word i mean) -  icon representation of a factory?01:41
arossdotmeor pictures  along the lines of portable computer product life cycle, designed/plotted (planned) obsolescence that you have came across?01:44
kristianpaulmoin14:48
whitequark<furan>Ihttps://github.com/cseed/arachne-pnr Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the Yosys [0] synthesis suite for example. It currently targets the Lattice Semiconductor iCE40LP/HX1K FPGA [1].19:04
kristianpauloh19:05
kristianpaulwait wait, so this is another HDL ?19:05
Action: kristianpaul clicks19:06
kristianpaulis that private whitequark ?19:06
kristianpaulnm19:07
whitequarkno, not a HDL19:07
whitequarkthis is a PAR for lattice19:07
kristianpaulbut yosys uses abc i think for PAR no?19:07
whitequarkabc is for ASIC19:08
whitequarkthere was no OSS PAR for FPGAs so far19:08
whitequark(fpgatools don't count)19:08
kristianpaulsure not fpgatools is just foorplan19:09
kristianpaulhmm i tought yosys was doing PAR for its ice40 lib..19:11
kristianpaulstill too early to speak, he commits everday..19:11
whitequarkwell, it already works to a degree19:34
--- Thu May 28 201500:00

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