#qi-hardware IRC log for Tuesday, 2013-10-22

--- Tue Oct 22 201300:00
wpwraknice: developer gets approached by state spies who want to hire him, blogs about it: http://www.thoughtcrime.org/blog/saudi-surveillance/19:32
eintopfwpwrak: hi :)19:49
wpwrakeintopf: heya ! you know how developers calculate time ... given an estimate of X, add one, them multiply by two, and convert to the next higher unit19:56
wpwrakeintopf: so if i say "i'll review it tomorrow", that really means in about four weeks :)19:57
eintopfit's ok19:57
eintopfi made now the "easy to review trivial cleanup patchstack"19:57
eintopfmaybe you can review this19:58
eintopfthen I add your Acked, Reviewed19:58
eintopfthen netdev19:58
eintopfmy internet is damn slow today19:58
eintopfwpwrak: https://dl.dropboxusercontent.com/u/5815386/IMG_20131022_215934.jpg development setup, just ignore the dust :D20:11
eintopffirst the contiki stick, then two of your atusb which controlled via qemu20:11
apeleteHello there20:12
kristianpaulHi :)20:14
apeletelarsc mth: added some logging in ep_config_from_hw() in musb_core.c where the usb endpoints scanning happens -> http://paste.debian.net/60583/20:15
apeletekristianpaul: Hi :)20:16
apeletelarsc mth: turns out the scanning is failing on the first musb_read_fifosize() call in there:20:17
apelete[    1.870000] musb-hdrc: epnums = 1 | musb_num_eps = 620:17
apelete[    1.880000] musb_read_fifosize: musb_readb failed20:17
apelete[    1.890000] musb-hdrc: musb_read_fifosize failed20:17
apelete[    1.900000] musb-hdrc: missing bulk20:17
apeletemusb_read_fifosize() in turn calls musb_readb(), which fails.20:18
apeleteseems pretty bad since musb_readb() is trying to read hardware registers, if I'm not mistaken20:20
apeletelarsc mth: is possible the something may be missing or badly declared in platform data for the registers not to be readable ?20:23
mthis the udc clock running?20:27
apeletehow do I check that ?20:29
mththere is a register that contains the mask bits for all the clocks; printing the contents of that register should tell you whether it's enabled or not20:29
mthclock gate register iirc20:30
apeleteok, in the init function I'm doing:20:30
apeleteclk = devm_clk_get(dev, "udc");20:30
apeleteif (IS_ERR(clk)) {20:30
apeleteint ret = PTR_ERR(clk);20:30
apeletedev_err(dev, "Failed to get clock: %d\n", ret);20:30
apeletereturn ret;20:30
apelete}20:30
apeleteglue->clk = clk;20:31
apeleteclk_enable(clk);20:31
apelete 20:31
apeletethought that was enough to get the clock running20:31
apeletewill check the register you're talking about20:31
mththere was something about clk_enable being replaced in recent kernel versions20:39
mthlarsc will know more about it20:39
mthI don't know if clk_enable won't work anymore or is just wrong in theory20:39
mththat fragment looks ok, but it's useful to double check, just in case the enable failed, the code gets executed in an unexpected order, something disabling the clock after it got enabled etc20:40
apeleteok, couldn't find out how to check clock gate register so will start by adding checks for clk_enable in case it fails during init20:43
mthsimply casts its address to an unsigned int * and dereference that21:09
mthaddress being the virtual address of the register, which is 0xB.......21:10
mthphysical address is 0x1......., add 0xA0000000 for kseg121:10
apeletemth: not sure about what you're saying. should I cast the return value of devm_clk_get() ?21:15
mthno, the address from the programming manual, inside the musb endpoint scanning code21:16
apeleteha21:17
apeleteok, will look into the programming manual and try to do that from inside the musb endpoint scanning code21:18
apeletemth: found it:21:26
apeleteThe Clock Gate Register (CLKGR) is a 32-bit read/write register that controls the CLOCK GATE21:26
apeletefunction of peripherals. It is initialized to 0x00000000 by any reset.21:26
apeletethe udc bit seems to be 11th bit according to programming manual21:27
apeletemth: ok now, I added the folloqing lines at the beginning of ep_config_from_hw():22:05
apeleteu32 * clk_gate_reg = 0x10000020 + 0xA0000000;22:05
apeletepr_debug("%s: clk_gate_reg value is %x\n", musb_driver_name, &clk_gate_reg);22:05
apeleteduring boot I get:22:05
apelete[    1.940000] musb-hdrc: clk_gate_reg value is 81c25b1822:05
apeleteaccording to programming manual, udc bit in gate clock register is 11th bit (counting from 0)22:06
apeletemth: if what I did seems correct to you, then 11th is set to 1 in hex number 81c25b1822:08
apeletemth: programming manual says:22:09
apelete0: udc_hclk always running, dont stop22:09
apelete1: Only udc enters suspend mode, udc_hclk22:09
apeletehas been stopped . if the bit is 1 and udc22:09
apeletedoesnt enters suspend mode, udc_hclk22:09
apeletealways runs22:09
apeletemth: so I guess the clock is not running then, as you hinted. is this correct ?22:10
mthapelete: you're taking the address instead of dereferencing22:16
mthto be on the safe side, adding "volatile" to the type would be good, but if you read it only once that doesn't really matter22:16
apeletecrap, didn't noticed I was writing & instead of * there...22:17
apeletechanging22:27
apeletepr_debug("%s: clk_gate_reg value is %x\n", musb_driver_name, &clk_gate_reg);22:27
apeleteto22:27
apeletepr_debug("%s: clk_gate_reg value is %x\n", musb_driver_name, *clk_gate_reg);22:27
apeleteI now get:22:27
apelete[    1.960000] musb-hdrc: clk_gate_reg value is eb5822:27
apeletemth: correct value now, 11th bit still set to 1 it seems22:28
mth11th bit or bit 11?22:28
mth(since bit 11 is the 12th bit from right)22:28
apeletebit 11, sorry22:28
apeletebit 11 indeed, counting from 0 it's the 12th bit :-)22:29
apeleteprogramming manual says: Bit -> 11, Module -> UDC, Descrption -> "0: udc_hclk always running, dont stop22:31
apelete1: Only udc enters suspend mode, udc_hclk22:32
apeletehas been stopped . if the bit is 1 and udc22:32
apeletedoesnt enters suspend mode, udc_hclk22:32
mthyes, it's different from the other clock gate bits22:32
mthso it being 1 might not be a problem, but you could try forcing it to 0 to see if that changes anything (just for testing)22:32
mthor print the sleep control reg22:33
apeletemth: here it is:22:45
apelete[    1.920000] musb-hdrc: sleep_control_reg value is 154022:45
apeletemanual says: Bits -> 15:8, Name -> 01ST, Description:22:46
mthok, bit 6 is 1, so udc is not suspended22:46
apeleteok22:47
apeleteso what do you think is going on then ?22:47
mthno idea; the clock being disabled was my best guess22:48
mthtry looking inside the method that reports the read error, to see at what point it decides the read failed22:48
mthalso check whether the old driver does any kind of endpoint scanning22:48
mthor if it doesn't, what addresses it uses to program endpoints22:49
apeleteok22:49
apeletemth: thanks for the help all along, that was very helpulf (and supportive) :)22:50
mthyou're welcome22:50
apeleteI might feel sleepy tomorrow at work (it's getting late here), but it was worth it. learned a few things tonight :)22:53
--- Wed Oct 23 201300:00

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