| K0D3R | hello | 02:25 |
|---|---|---|
| K0D3R | where can I buy a Milkymist | 02:25 |
| K0D3R | ? | 02:25 |
| K0D3R | sharism.cc is down | 02:29 |
| K0D3R | the links to hackabe-devices returns 404 | 02:32 |
| whitequark | maybe you should ask wolfspraul | 02:47 |
| K0D3R | whitequark: who is wolfspraul | 03:28 |
| K0D3R | ? | 03:28 |
| whitequark | wolfspraul: K0D3R wants to buy an M1 | 04:15 |
| wolfspraul | wow nice! | 04:18 |
| whitequark | but sharism.cc is down | 04:19 |
| wolfspraul | there were some hickups but it should be back up | 04:20 |
| K0D3R | wolfspraul: hey! | 04:20 |
| whitequark | wolfspraul: oh. some folks here decided that you've had "enough of it" | 04:21 |
| whitequark | I'm glad that's not true | 04:21 |
| K0D3R | wolfspraul: whitequark said that I should talk to you | 04:22 |
| wolfspraul | sure that's nice | 04:22 |
| K0D3R | how can I buy a Milkymist? | 04:22 |
| wolfspraul | just at sharism.cc | 04:22 |
| wolfspraul | we ship from Taipei and it should be with you in 3-4 days or so, depending on where you are | 04:23 |
| wolfspraul | we have shipped a lot to US, Australia, Europe | 04:23 |
| K0D3R | but it is down | 04:23 |
| K0D3R | I meant: sharism.cc is down | 04:23 |
| whitequark | K0D3R: up for me already | 04:23 |
| K0D3R | whitequark: oh! it's up now! thanks! | 04:24 |
| K0D3R | someone turned the switch on! :) | 04:25 |
| K0D3R | wolfspraul: do you ship it yourself? | 04:26 |
| wolfspraul | whitequark: thanks, I think I answered all his questions | 05:09 |
| wolfspraul | thanks for making the connection... | 05:09 |
| whitequark | wolfspraul: you're welcome :) | 05:46 |
| Fallenou | hi wolfspraul , good that sharism.cc is back on :) | 06:21 |
| wpwrak | kristianpaul: not sure what you mean with moving things between application and kernel. i think an fpga should probably be assigned to a single task (process or group of cooperating processes), at least for now. | 12:51 |
| wpwrak | if someone can figure out a way to actually multitask with them, even better. so that's another item for the research topic list :) | 12:52 |
| wpwrak | (multitask) in this case, have independent tasks using them, e.g., a video game and a bitcoin miner | 12:54 |
| paul_boddie | wpwrak: How did you do the video for http://en.qi-hardware.com/wiki/UBB-VGA (hint: not very descriptive page)? Is it all generated in the CPU's "spare moments" or is there some kind of backing store? | 14:02 |
| wpwrak | paul_boddie: you may find this page more useful: http://downloads.qi-hardware.com/people/werner/ubb/vga/web/ | 14:22 |
| wpwrak | and it's unfortunately not in "spare moments". the cpu is working on it full-time. well, most of it is spent waiting for DMA, but it wouldn't be easy to let it do useful work instead of waiting. | 14:23 |
| paul_boddie | I guess the aim is to do live screen updates, rather than just push out still images, or am I wrong? | 14:27 |
| paul_boddie | The reason why I ask is because you were discussing FPGAs and the whole thing reminds me of some ULA-like circuitry from the microcomputer era that I've become interested in over the past year or so. | 14:28 |
| Action: paul_boddie looks at http://downloads.qi-hardware.com/people/werner/ubb/vga/web/ | 14:29 | |
| wpwrak | the initial aim was just a proof of concept. see how far i can take it in terms of image quality/resolution. that works pretty well now. but it only does still images. | 14:31 |
| wpwrak | for live updates, you'd have to move the DMA control and hsync processing into an interrupt handler and then time interrupts such that you never miss the time for the next line. (the cpu needs to intervene for each line, because the operation stalls the mmc controller) | 14:34 |
| paul_boddie | It's a shame that the 8:10 slot isn't like the expansion bus on various computers (or Firewire, maybe). | 14:35 |
| wpwrak | (and the mmc controller also spits out some "noise" that you don't want in the image. maybe you could work around this, though) | 14:35 |
| wpwrak | well, it's quite flexible | 14:35 |
| paul_boddie | In the sense that with various microcomputers, you could make peripherals that can access memory and stuff like that. | 14:36 |
| paul_boddie | I guess all that is formalised in various standard interfaces, though, but not for the 8:10 port. | 14:37 |
| wpwrak | way too complex :) and you don't want to expose a memory bus. not since 1990 or so, when they just started to get too fast for such things | 14:39 |
| paul_boddie | I was just thinking of the DMA aspect, but as I noted, I imagine that various standard interfaces provide that, and Firewire is notorious for doing so. | 14:41 |
| paul_boddie | A kind of slow-motion access to memory would be cool, but I agree that it would complicate things. | 14:42 |
| wpwrak | yeah, but that also means that you need a firewire controller on your boards. i prefer the simplicity of ubb :) | 14:42 |
| wpwrak | what would be nice is to have a cpld or small fpga between cpu and 8:10 card(s). that way, you could implement your own protocols. | 14:43 |
| paul_boddie | I guess you continuously drive the display instead of transferring a bitmap for output, then. | 14:43 |
| wpwrak | well, you have to continuously generate the video signal. even though the screen would probably have an internal frame buffer, it's not used in that way. and of course, even less so with vga. | 14:45 |
| paul_boddie | Yes, I have a small LCD panel for use with Arduino that probably has a more powerful CPU and more internal memory than the ATmega. | 14:46 |
| paul_boddie | For the video signal, I'd have thought we would be in FPGA territory. | 14:47 |
| wpwrak | what ubb-vga does is that it precomputes the bit pattern for the image. then it sends this pattern in an MMC block transfer. at the beginning of a line, the cpu needs to generate a start bit for MMC and mask the output for the mmc command (which would look like noise in the image). | 15:03 |
| wpwrak | (look like noise. or, worse, throw off the image position detection in the screen) | 15:04 |
| kristianpaul | wpwrak: yes basically what you said i meant | 15:46 |
| --- Tue Mar 5 2013 | 00:00 | |
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