| wolfspraul | a small fpgatools update - I think my next target after blinking_led will be the j1 mini-core | 02:24 |
|---|---|---|
| wolfspraul | hopefully I can finish the blinking_led in about 1 more week | 02:24 |
| wolfspraul | that's all :-) | 02:25 |
| wpwrak | whee ! the blinking LED is the creation of life in a new universe. a core is merely evolution :) | 02:34 |
| wolfspraul | btw this is what the .c looks like now after your model->rc cleanup... https://github.com/Wolfgang-Spraul/fpgatools/blob/master/blinking_led.c | 02:57 |
| wolfspraul | that is the final version of blinking_led, only that the engine underneath does not yet generate a working bitstream... | 02:58 |
| wolfspraul | (and at the top I added a little verilog equivalent for comparison and documentation) | 02:58 |
| wolfspraul | oh actually, I just notice it's not the final .c yet. the clock network is there, but some other networks are missing... | 03:01 |
| wolfspraul | more work in fnet_autoroute() :-) | 03:01 |
| wpwrak | hmm, quite a bit of redundancy | 03:10 |
| wpwrak | may look better if you use static initialization for logic_cfg | 03:11 |
| wpwrak | oh, and why y before x ? if they're coordinates, that seems rather confusing | 03:12 |
| wolfspraul | yes I know, but there's a lot of fpga literature and sources that do that, although in general coordinates are confusing in the fpga world | 03:13 |
| wolfspraul | at the beginning I was thinking about this. x/y in the bottom left, x extending to the right and y upwards | 03:14 |
| wpwrak | ah, i see. historical convention then. | 03:14 |
| wolfspraul | but then I followed what looks like at least the largest 'convention' | 03:14 |
| wolfspraul | which is y going downwards (0 at the top), and y before x | 03:14 |
| wolfspraul | but then, you find everything, because i guess everybody stumbles upon this and then partially goes this or that way | 03:15 |
| wpwrak | heh :) | 03:15 |
| wolfspraul | oftentimes in the same sources you find some coordinates where y extends downwards, and others where it extends upwards | 03:15 |
| wolfspraul | yes, let's just say 'convention', although I am just trying to find a convention where maybe there is no convention | 03:16 |
| wpwrak | maybe you should just switch to polar coordinates :) | 03:16 |
| wpwrak | there you are ;-) | 03:16 |
| wolfspraul | y before x, y increasing downwards, x increasing rightwards | 03:16 |
| wolfspraul | at least fpgatools has only 1 coordinate system, some other popular fpga tools have >10 :-) | 03:16 |
| wolfspraul | static init for logic_cfg, sure | 03:17 |
| wolfspraul | I am not focusing on that 'higher' layer right now that much | 03:17 |
| wpwrak | (10 dimensions) sounds like string theory :) | 03:17 |
| wolfspraul | well the different types/categories of things each have their own coordinates | 03:17 |
| wolfspraul | so X2 'logic col' is one right of X1 'logic col' | 03:18 |
| wolfspraul | but there may be a X0 bram col in between :-) | 03:18 |
| wpwrak | (static init) actually, i see that it's more complicated since you carry over a lot of information from step to step. you'd probably need some sort of preprocessor. | 03:18 |
| wolfspraul | yes | 03:18 |
| wolfspraul | no need right now, I focus on the engine underneath | 03:18 |
| wolfspraul | that .c is just the tip of the iceberg | 03:18 |
| wolfspraul | later on maybe I find a way to write a bison parser or so, or we plug fpgatools in as an iverilog backend... | 03:19 |
| wolfspraul | it does look a lot cleaner now though | 03:19 |
| wolfspraul | without the if(rc) checks | 03:19 |
| wpwrak | yeah, it's pretty smooth reading | 03:20 |
| wolfspraul | some more networks missing, the connections between the luts, and the outgoing led wire... | 03:21 |
| wolfspraul | maybe 1 week is too optimistic, he | 03:21 |
| wolfspraul | first get the led to blink... | 03:21 |
| wolfspraul | thanks for looking over it... | 03:22 |
| wpwrak | i see that you often have (y, x, idx) groups. maybe they could go into a struct, to reduce the number of arguments ? | 03:22 |
| wolfspraul | yes | 03:24 |
| wolfspraul | the temptation of C++ looms over it, but we shall resist... | 03:24 |
| wpwrak | all the good things C++ tempts you with you can also do in C :) | 03:25 |
| wolfspraul | when it's time to bury the project and declare it a failure, I will introduce C++ templates and operator overloading one month in advance... | 03:25 |
| wolfspraul | then we can blame C++ | 03:26 |
| wolfspraul | that's the secret plan B here... | 03:26 |
| wpwrak | maybe that's why C++ is so popular | 03:27 |
| wpwrak | well, its star seems to be sinking a bit. maybe developers have gotten better and don't have quite so many failed projects to explain | 03:27 |
| mat146 | hey | 11:34 |
| mat146 | asus or acer? | 11:34 |
| mat146 | http://allegro.pl/ShowItem2.php?item=2851480171 http://www.x-kom.pl/p/121329-notebook-laptop-15,6-acer-tm5744-i3-380m-4gb-500-dvd-rw.html | 11:34 |
| LunaVorax | Hi | 13:07 |
| kristianpaul | hello | 13:17 |
| --- Fri Dec 14 2012 | 00:00 | |
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