#qi-hardware IRC log for Sunday, 2012-08-12

--- Sun Aug 12 201200:00
valhallaI've flashed the latest uboot (2012-07-11) on the nanonote and now it isn't booting from SD anymore (I press M+power it cycles inside uboot until I release M, and then starts from the nand)13:37
xiangfuvalhalla, sorry about the bug, the code is same, after we update the gcc/uclibc, it woldn't  boot from sd anymore13:42
kristianpaul:o13:43
xiangfuvalhalla, please revert back to : http://downloads.qi-hardware.com/software/images/NanoNote/Ben/2011-11-13/openwrt-xburst-qi_lb60-u-boot.bin13:43
xiangfuvalhalla, I will try to fix that bug next few days. (I am slow)13:43
xiangfukristianpaul, Hi13:46
xiangfukristianpaul, I have one fpga question.13:46
kristianpauloh sure13:47
kristianpaulHi !13:47
valhallaxiangfu: ok, so it is a known problem, thanks13:48
xiangfukristianpaul, here is a simple verlog code.13:48
xiangfukristianpaul, if I don't connect any oscillator, the 'y'(which I connect a led) will flash. where is the clock from?13:50
kristianpauli think i missed your pastebin..13:50
kristianpaulyou dont need an oscillator all times, it varies from what you want to synthesize13:51
xiangfukristianpaul, here: http://pastebin.com/kLTn9JS213:52
kristianpauland the .ucf? 13:54
xiangfukristianpaul, http://pastebin.com/bA6sxiKj13:54
xiangfukristianpaul, there is nothing connect to P55. 13:55
kristianpaulokay but is unconeected?13:56
kristianpaulnot even grounded?13:56
xiangfuno ground. nothing. 13:56
kristianpaulwich would made me think thats where you clock came from :)13:56
kristianpaulah13:56
xiangfuthat is my question. I use jtag load the bitstream to chip.13:57
kristianpauli *think* your "clock" just came from the static,13:58
kristianpaulif you have a scope around you could try to see the LED input from fpga13:59
kristianpauli bet is not that stable clock at all13:59
kristianpauljtag have its own clock, not to be related with any other clock source used on your verilog project14:00
kristianpaulxiangfu: u there?14:00
xiangfuyes14:00
kristianpaulwhy you not try to ground that P5014:01
xiangfuyou mean P55?14:01
kristianpaulah yes sorry14:01
xiangfukristianpaul, here is my board: http://en.qi-hardware.com/wiki/Mini-slx914:01
kristianpaulfrom the verilog it self or externally14:02
xiangfukristianpaul, all pins are not ground . I only connect the pins I am using.14:02
kristianpaulwell, in your UCF file you claim that will use that P55 14:02
kristianpaulyou dint.. but you either ground it..14:02
kristianpaulso this could lead to unknow behavior i think14:03
kristianpaulah nice board !14:03
kristianpaulxiangfu: what i said answer your question?14:04
xiangfu(lead to unknow behavior i think). ok. 14:05
kristianpauli'm not 100% certain14:05
kristianpaulbut just what i learn from milkymist, ie this https://github.com/milkymist/milkymist/blob/master/boards/milkymist-one/rtl/system.v#L110314:05
xiangfuok. I have 40M,20M,8M,6M,2M  oscillator14:06
kristianpaulmade me think if not using it you should ground it "assign mc_clk = 1'b0;"14:06
xiangfuI try to connect 40M/20M to P55.14:06
kristianpaulin your case externally14:06
kristianpaulwhat happen when you connect it?14:07
xiangfubut the mc_clk is output. not like my P55(input)14:08
kristianpaulahh true14:08
xiangfukristianpaul, nothing happen. I keep get 0 from 'x'14:08
xiangfuI also not sure if my little  oscillator board is working.14:08
xiangfuI just connect 3.3v and GND to the osc. and connect one wire to P55.14:09
kristianpaulyou have scope?14:09
xiangfufrom the datasheet. it says the userclk must be short then 0.8cm (Stubs, if necessary, must be shorter than 8 mm (0.3 inches).)14:10
kristianpaulhmm14:10
xiangfukristianpaul, I have a usb scope. dso2090. but after update my system the 'openhantek' command not working any more.14:10
wpwrakyour little board probably violates a 1000 design recommendations already. what's one more ? ;-))14:11
xiangfuwpwrak, :-)14:11
kristianpaulxD14:11
wpwrakjust try to run things at slow clocks and slow I/O (QUIETIO sounds good), then you should be able to get away with most things.14:11
xiangfuwpwrak, yes. I have 40M/20M osc on my desk. the 8M/6M/2M osc is one the way to my desk. :)14:14
xiangfuhope the 2M is slow enough. 14:15
xiangfuthe hdl code is interesting. is not running line by line. once power on. all lines code are running. :)14:16
kristianpaulyup14:16
kristianpaulas it is sinthesized14:17
xiangfuwpwrak, I read the QUIETIO is better for LED. 14:17
xiangfuin fact I am not question understand. when should i use QUIETIO/SLOW/FAST14:17
xiangfukristianpaul, wpwrak : after I remove 'clk/P55' the led still flashing.  the code is like: http://pastebin.com/rYb33fVS14:18
kristianpaulhow you connected a and b?14:19
xiangfuto 3.3v14:20
kristianpaulbtw your counter missed a reset.. guess not matter much here but just to get used to use it :)14:21
kristianpaulbut is flashing under the espected freq?14:23
kristianpaulif you ground 1 or b, it should stop14:24
kristianpauls/1/a14:24
xiangfuit's flashing at expected freq.14:25
xiangfuif I ground b or a to GND, it will stop. 14:25
xiangfuall works like there is a clock somewhere.14:26
kristianpaulthe counter :-)14:28
kristianpaulthats your clock source14:32
xiangfuwhat you mean?14:34
kristianpaulyour hdl code describe something that looks like a counter14:34
kristianpaulyou have the build log at hand?14:37
xiangfukristianpaul, I can rebuild it now. wait14:38
xiangfukristianpaul, here is the full log: http://pastebin.com/6aGMku8k14:42
kristianpaulah look line 11114:45
kristianpaulthat is a loop aka your clock source :-)14:45
xiangfustill don't understand :(14:52
kristianpaulyou could make a clock using combinational logic14:53
kristianpaulthats a circuit input is fed by it own output14:53
kristianpaulso is a loop14:54
xiangfuok14:54
xiangfukristianpaul, thanks. I got it.14:54
kristianpaulsure? ..14:54
kristianpauli still thinkking.. well i dont know how xst sinthesized it..14:55
xiangfuI got some idea. not very clear. my goal is connect the external osc. this is not very important for now. :)14:55
kristianpaulah ok14:55
kristianpaulyou could even made an osc of the fpga, using a couple not gates in a loop :)14:55
xiangfukristianpaul, is there some code? :)14:56
kristianpaulsecond14:57
kristianpauloops, better minute i'm looking14:57
kristianpauldamn, so far i just found this ilustration http://goo.gl/oibwQ15:13
xiangfusure I just take a look. and learn15:15
Fallenouxiangfu: hey :) experimenting some fpga design ? :)15:28
LunaVoraxhi15:46
Jay7http://youtu.be/ikD_3Vemkf020:13
Jay73d tracking interface20:14
Jay7even so: http://makeprojects.com/Project/A-Touchless-3D-Tracking-Interface/2233/1#.UCgOnztlyXI20:14
--- Mon Aug 13 201200:00

Generated by irclog2html.py 2.9.2 by Marius Gedminas - find it at mg.pov.lt!