#qi-hardware IRC log for Wednesday, 2012-05-30

wpwrak(sigrok) looks pretty cool00:15
Action: kristianpaul needs try its avnet hacked for sump with sigrok00:25
kristianpaulwpwrak: you're right was matter of fixing some naming from guess russian characters for something more utf-8 friendly00:25
kristianpaulthe eeschema loading error from yday00:26
wpwrakhah ! :)00:26
wpwrakbabylonization is a source of endless fun00:26
kristianpaul├▒es !!00:27
kristianpauldammit i cant not run decently even gnuradio to live decode fm..00:28
kristianpaulthats a good excuse to get and more than two cores laptop.. not now but later perhaps00:29
kristianpaulor better excuse to hack more in to hdl :)00:29
qi-bot[commit] Werner Almesberger: modules/qfp-gen.fpd: further improvements (WIP) (master) http://qi-hw.com/p/kicad-libs/20b7c5f00:54
cladamwwpwrak, can add XOR or like "if" expression under frame ?02:29
cladamwwpwrak, if no, i think it's a good feature to add in the future. :)02:29
wpwrakthere are two ways to make an "if":02:30
wpwrakloop if = 1,expr02:30
wpwrakand  set ?expr = 1  /* or whatever value would be "true". can also be a string */02:31
wpwrakerr, s/?expr/?var02:31
wpwrakif you need an expression, the 2nd form would be:02:31
wpwrakset tmp = expr02:31
wpwrakset ?tmp = value02:31
wpwrakno, wait ...02:32
wpwrakyeah works. looks weird but it's okay.02:34
wpwrakthe   set ?var = value  form needs the latest fped from git. the older  loop var = 1, one_or_zero  form also works if old versions of fped02:35
wpwraks/if old/with old02:36
wpwraki think i need some sleep :(02:36
cladamwwpwrak, aha ... tks a lots. need to practice. 02:39
qi-botThe build was successful: http://fidelio.qi-hardware.com/~xiangfu/build-nanonote/openwrt-xburst.full_system-20120528-2138 03:35
qi-bot[commit] Adam Wang: INFO: clean up by order (master) http://qi-hw.com/p/kicad-libs/e3556ca04:06
qi-bot[commit] Adam Wang: Merge branch 'master' of projects.qi-hardware.com:kicad-libs (master) http://qi-hw.com/p/kicad-libs/8b151f104:06
qi-bot[commit] Adam Wang: eus.fpd: added new EUS for TI PTH04000WAH footprint (master) http://qi-hw.com/p/kicad-libs/4cc64c904:07
cladamw_wpwrak, about (if) expression, i saw example from sot.fpd but still don't fully understand how to use two boundaries to 'filter' those pins I don't want to show them.09:06
cladamw_wpwrak, for example I did this: http://projects.qi-hardware.com/index.php/p/kicad-libs/source/tree/master/modules/eus.fpd09:07
cladamw_wpwrak, there's pin 5 and 6 are not in proper order same as pins_bottom frame, (i.e. a spindle coordinates pins vectors), I've tried to learned to disable ( i.e. multiply by an index) pin 6, 7 vectors but not in success though. In the end, I used a very stupid way to split two quadrants individually then finished. :-) The codes are not smart at all. So if you have available time, could you show me an alternative codes by 09:15
cladamw_using "if" expression to optimize codes ? :-O09:15
cladamw_i've been loving your this Fped, it's not about efficiency to help work or not, it's about to apply/scrap math together from schools.  :-)09:18
xiangfujivs, from the build host also failed to build guile2 :(11:39
wpwrak"death rattle" ?15:59
qi-bot[commit] Werner Almesberger: ircstat/ML: April 2012 figures (belatedly - forgot to commit) (master) http://qi-hw.com/p/wernermisc/bd8c84d16:07
qi-bot[commit] Werner Almesberger: ircstat/stat: move source file and filter to a variable (master) http://qi-hw.com/p/wernermisc/70b01eb16:07
qi-bot[commit] Werner Almesberger: separate dumping of hierchy rules from dumping of fields (master) http://qi-hw.com/p/eda-tools/b6a4a8016:07
qi-bot[commit] Werner Almesberger: new option -N to override file names in diagnostics (for regression testing) (master) http://qi-hw.com/p/eda-tools/60de30c16:07
qi-bot[commit] Werner Almesberger: add regression test infrastructure (master) http://qi-hw.com/p/eda-tools/88ad25e16:07
qi-bot[commit] Werner Almesberger: test/hierfld: field definitions in hierarchy (master) http://qi-hw.com/p/eda-tools/c24da0216:07
qi-bot[commit] Werner Almesberger: new option -v to control verbosity level; move hierarchy dump from parser to boom.c (master) http://qi-hw.com/p/eda-tools/59d21e616:07
whitequarkcan I ask a question about cpus/fpgas?18:52
Aylayou may18:53
whitequarklet there be an ARM and an FPGA18:54
whitequarkFPGA sits on ARM's external bus18:54
whitequarkARM's bus controller is technically external, but it's clocked by the same signal as the FPGA18:54
whitequarkcan bus be used as a synchronous one from within the FPGA18:54
whitequarks,technically external,technically asynchronous,19:01
larscwhitequark: what do you mean by technically asynchronous20:14
kristianpaulclocked but this actually mean same bus speed i guess20:36
kristianpaulor... ?20:37
kristianpaulwhitequark: you could implemented a dual ported stam on the fpga that "wires" to arm bus i guess support slave memory interface20:38
kristianpaulwell but that wasnt a good asnwer to your question :)20:39
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