#qi-hardware IRC log for Thursday, 2011-08-25

qi-bot[commit] Xiangfu Liu: not working without asound.conf, asound.conf make MIC not working (master) http://qi-hw.com/p/openwrt-packages/7d202ed00:10
qi-bot[commit] Xiangfu Liu: nanonote-files: add hwclock --hctosys when shutdown (master) http://qi-hw.com/p/openwrt-packages/b68539701:09
wpwrakinteresting treatise on how the structure of names varies across cultures: http://www.w3.org/International/questions/qa-personal-names02:27
kristianpaulsteve|m: nice sandpaper work with c123 :)03:27
kristianpaulreally interesting to realize a 3 layer phone 03:31
kristianpauljust in case not body here follow rss from osmocom track http://www.steve-m.de/pictures/compal_e88/03:31
kristianpaulnot all body**03:31
wolfsprauloh another rss I don't know about03:46
wolfspraulkristianpaul: if you see any good rss missing in the qi planet, please let me know03:46
wolfspraulwow this is a nice job!03:47
wolfspraulkristianpaul: what is the rss url?03:49
kristianpaulnot sure if qi planet fits well with trac rss.. but you asked03:50
wolfspraulah trac rss, yeah, probably not so good03:50
wolfspraulbut that's a really nice sanding job there03:51
kristianpaulhttp://planet.osmocom.org/rss20.xml just in case you were aware of03:51
wolfspraulwe should spread the word how easy it is to see inside a pcb03:51
wolfspraulsince some people prefer to make a big fuss about that03:51
kristianpaulactually i still dont get full understand of procedure or at least sandpaper ref..03:52
wolfspraulsteve did a really wonderful job there, I'm wondering how many hours it took him03:52
wolfspraulit's super easy, you should try yourself :-)03:52
wolfspraultake some old broken electronics03:52
wolfspraulkristianpaul: last time steve|m said he started with corning 120 paper, and once he started to see the next layer, he switched to corning 400 for polishing03:54
kristianpaulso is just hold PCB and start sanding?03:54
wolfspraulfor that amount of layers steve did there (compal 88), I would estimate a total working time of ca. 10 hours though03:54
wolfspraulsteve said "using a few rows of gaffer-tape as an underlayment, since the non-adhesive site is quite resistant to the sandpaper"03:55
wolfspraulso he just puts the tape on his wooden desk, then the pcb on top, then work starts :-)03:56
wpwrakmaybe an even easier approach would be to mill off a little, take a picture, mill off 50-100 um more, etc.03:58
wpwrakwould of course be slower, but it would be all automated03:59
kristianpaulyou can mill that resolution wow !04:00
wpwrakshould take about 1/2 hour per layer. ~20 layers. so it's an overnight job.04:01
wpwrakkristianpaul: 0.1 mm isn't particularly precise :)04:01
kristianpaulI'll say that when some day get a milling machine...04:02
wpwrakyou need something that blows away the dust before taking the picture, though04:02
wpwrakmy mill should be able to do about 25 us04:03
steve|mkristianpaul: hehe, thanks08:54
steve|mkristianpaul: it took ~4 hours, this time I etched off the layers I already scanned, and only sanded the material between the layers08:55
steve|mworked quite nice08:55
DocScrutinizersteve|m: duh, what you're doing?10:14
DocScrutinizernm, I read backscroll10:20
DocScrutinizerhttp://www.steve-m.de/pictures/compal_e88/07_front_layer1.jpg  WTF!?! spark gaps - that's stone age10:24
steve|mDocScrutinizer: what do you mean exactly?10:26
DocScrutinizerby sparkgaps? the structures left to the LCD connector pads10:26
steve|mDocScrutinizer: ah right, for ESD discharge10:27
DocScrutinizeryou *may* use spark gaps, given it's 100% additional and just because we get it for free, and also only if it's properly covered by protective varnish (which is the case here it seems)10:28
DocScrutinizerbut never use spark gaps as a "replacement" for proper tranzorb/varistor ESD protection10:29
DocScrutinizerhttp://www.steve-m.de/pictures/compal_e88/05_front_layer3.jpg is kinda hard to decode. You'd need a second board to do the front layers on that10:31
DocScrutinizerthinking about spark gaps: you mustn't use them on unprotected outer layer as random dirt may collect between the spikes and create a short. But then when you cover the spark gap with protective varnish (the green stuff) it's no longer a free air spark gap and your break down voltage rises massively, thus rendering the spark gap useless for the intended purpose10:37
DocScrutinizerI'd love to learn there's a software that can scan and parse the layers as of  http://www.steve-m.de/pictures/ (nice job steve|m ! :-D) and reverse this into a semi-proper schematic10:39
DocScrutinizerI've done that sort of RE on somewhat simpler layouts and it's a *real* nightmare10:41
DocScrutinizerbut I guess you probably could create s schematics that looks exactly like all the layers in one stack, and just create connections between traces where due - e.g on vias10:44
DocScrutinizersth like eagle shouldn't mind about weird schematics layout. Then you can "de-route" it10:44
DocScrutinizerand fill in proper component symbols10:45
Action: DocScrutinizer idly ponders about floodfill algo of painting programs10:48
DocScrutinizerhmmm, a semi-smart algo: pic an arbitrary component pin; floodfill topmost layer trace; when floodfill algo hits a via, start a new floodfill on layers that have a trace in same location; when any of the floodfill processes hits another component pin, create a connection between starting pin and this pin in your schematics10:51
DocScrutinizerobviously the via processing needs to get smarter yet. There may be vias from e.g. layer 3 to layer 4 of a 6 layer PCB. Layer 1, 2, 6 may have traces at location of that via, but they have no via hole so are not connected to the via. Even worse: you *might* see 2 vias in same location: one from layer 1 to 2, one from layer 4 to 510:55
DocScrutinizerso via processing is: step up and down the layer stack until you find a layer that has no via hole in this location - this is the layer were your via ]ended10:57
DocScrutinizeryou *could* even think of via 1->2 and another one 3->4, but I guess that's no good practice10:58
DocScrutinizerand I don't know if PCB manufs can build such crazy stuff at all10:59
DocScrutinizerfirst doing all layer lamination, then care about vias - for sure the most easy manufacturing procedure11:03
DocScrutinizeror maybe they laminate 3 doublesided PCBs together and vias are done from front to back of either one doublesided PCB payer, or from front to back of PCB #1 and #2 lamitated (which was e.g from layer 1 to layer 4 then), then laminate the 3rd doublesided PCB (with its own front to back vias) and then you can create vias from layer 1 to 611:07
DocScrutinizerhttp://en.qi-hardware.com/wiki/Sciphone_Dream_G2#PCB_layers has via layer shots, which tell you if a via travels between the layer just removed and the one not yet visible. So including these steps our via problem is 100% solvable11:13
DocScrutinizer-> while floodfill algo stepping up/down the layers on a via, the via stops on a via layer that has no hole11:14
DocScrutinizersorry for flooding channel with my spam :-D11:15
kristianpaulno no, keep going ;)11:15
DocScrutinizerseems I'm done :-D11:16
DocScrutinizerone more note: you have to prepare your transparent stack of layers by tagging each component pin, and same time create the component in your ECAD schematics. So when you analyze the layer stack with that floodfill algo, the algo knows which two pins to connect in the schematics (e.g Eagle could do this via a list of macros to execute. The macro list could get created by your floodfill algo)11:26
DocScrutinizeradd in traveling-salesman distance evaluation for beauty of schematics' sake11:29
DocScrutinizerotherwise you get a lot of star topology trace networks, which might look really annoying11:30
DocScrutinizermaybe all that is moot, as I seem to recall at least one of all those Eagle, PADS and whatnot can backpropagate layout changes to schematics view11:32
DocScrutinizerso maybe it's just enough to import your RE'd layers to the layout view and *voila* schematics are born out of thin air (well almost, you still need to define the components)11:34
DocScrutinizerif you're curious about what's the deal with vias, a nice execise is to follow the TP018(?) marked "VBAT" in http://en.qi-hardware.com/wiki/Sciphone_Dream_G2#PCB_layers11:55
DocScrutinizerfrom starting on layer-6, it seems the via pattern changes from a four-dot to a 5-dot (as on die) on layer-5, then continues and connects to layer-2, and seems to me it even connects to layer-1 as well11:57
DocScrutinizerat least according to "9:2<->top vias"11:59
DocScrutinizererr "10:2<->top vias"12:00
DocScrutinizerand s/TP018/TP017/ sorry12:01
DocScrutinizerGND TP018 is even more puzzling12:03
DocScrutinizeranyway doing a complete RE of the schematics of a PCB the complexity of http://en.qi-hardware.com/wiki/Sciphone_Dream_G2#PCB_layers is probably a life's work (as you might go mad and die during this effort)12:21
DocScrutinizerunless you have some smart tools doing the "heavy lifting" for you12:22
DocScrutinizerwolfspraul: hey, http://en.qi-hardware.com/w/images/6/6b/Sciphone_G2_I10_v3_schematics.pdf p.4 "HANDSET MI COPHONE" has built-in buzz-fix :-D12:41
DocScrutinizerC409 ;-D12:42
DocScrutinizerand WTF they did to p.7 BT MT6601 U706:B4 TX_OUT ??? :-O12:48
wpwrakDocScrutinizer: i would first eliminate the concept of layers. just cut thin enough slices that you have at least one point between layers. the apply your flood fill to construct the netlist. after that, see how to convert it into something your schematics capture can use. e.g., auto-name nets, then put each component and just attach the nets as global labels. that way, you don't have to draw connecting lines. group things with a high 12:56
wpwrakdegree of connectivity close to each other. make some tool for global net renaming in the schematics (or each your EDA system the necessary tricks)12:56
DocScrutinizererr, sorry, you completely lost me. All I got was you tackle on a level that seems way more basic than mine12:58
DocScrutinizerI.E. I never draw connecting lines. I teach my floodfill algo to create a list of macros that make Eagle draw connection lines in a schematic that has only components to start with13:00
DocScrutinizerthis is probably what you meant by netlists13:01
DocScrutinizerEagle does auto-netlist-naming13:02
DocScrutinizerin interactive mode I click one component's pin and draw a rubberband line to an arbitrary 2nd pin, there I fix the rubberband and a new net gets created13:03
DocScrutinizerthis can get automated13:03
DocScrutinizervia macros13:03
DocScrutinizerconnect(U208:G4; R555:1)13:04
DocScrutinizerobviously you have to tag the pads for U208:G4 and R555:1 in your layers stack. Then the floodfill algo will create the macro as suggested 2 lines above13:05
DocScrutinizerexecute all the mocros generated by floodfill in Eagle, on a schematic that has only components placed on an empty sheet, and you get a schematic - though still an ugly one. Beautifying is rather easy in Eagle - that'S after all one of the topmost tasks of a EE CAD13:07
wpwrakyes, the list of nets and the things they connect to is called the netlist. this would be the principal output of your scanning. what you do then with it us a secondary step.13:07
wpwrakand don't use proprietary eagle ;-)13:08
DocScrutinizerI like Eagle a lot13:08
wpwrakit's still non-Free :)13:08
DocScrutinizerNB I didn't suggest to use PADS ;-P13:08
DocScrutinizerEagle is non-FOSS, it's free-as-in-beer for eurocard doublesided13:09
DocScrutinizerand has proper manuals and docs13:09
wpwrakyeah. a bit limited. not quite crippleware, but close ...13:10
DocScrutinizerbut sure it's irrelevant what frontend you run the macros to generate the netlist against13:10
wpwrakyup. the important thing is the netlist. the rest is just presentation :)13:11
DocScrutinizeryou need #) (automatic) preprocessing on your layer stack: clearly distinguish trace-copper pixels from "lawn" pixels, detect and mark via holes. #) Manual preprocessing: tag pads with component:pin labels. #) Floodfill starts "filling" from a not-yet-processed random pin, fills pixel by pixel, looks via layer above and below for a via tag for this position. If via detected: spawn a child floodfill for each layer in this direction of 13:20
DocScrutinizerstack that has either a lawn pixel with via tag or a copper pixel in this position, stop walking thru layer stack in this direction as soon as a via layer has no via tag in this position. // if the processed pixel has a pin tag, create a line in macro list to connect the origin pin where top level floodfill started to the pin we just found. /// start over with next unprocessed pin, pick it from a list of all pins/pads user marked in 13:20
DocScrutinizermaual step of preprocessing13:20
steve|mDocScrutinizer: "05_front_layer3.jpg is kinda hard to decode. You'd need a second board to do the front layers on that" <- how do you mean that?13:21
steve|mwhich front layer?13:21
steve|mI basically didn't fully remove the very thick finish from this layer and just painted it with textmarker to make it almost transparent13:23
steve|mbecause the stuff between the second and third layer was very thick and it took a long time to remove it13:23
steve|mthe next layer "beneath" that is http://www.steve-m.de/pictures/compal_e88/04_dbb_layer3.jpg13:24
steve|mso all layers are there, no second board needed13:24
DocScrutinizersteve|m: aah. Well I just meant the last layer is hard to work on, as it gets so thin. you better use a seconf 13:24
steve|mah right13:25
DocScrutinizersecond board and keep the back 3 layers while doing the front layers13:25
steve|myes, it's very thin13:25
steve|mI cracked it a bit in the middle13:25
DocScrutinizeror you glue the whole thing firmly to a basis, like a board or sth13:25
DocScrutinizerthat's probably how they did http://en.qi-hardware.com/wiki/Sciphone_Dream_G2#PCB_layers13:26
steve|mbut well, if you have all the pics you need using just one board, and wasting just one phone..13:26
steve|mwhy care13:26
DocScrutinizerthey couldn't do "12 : top silk" otherwise ;-)13:27
DocScrutinizerobviously "top silk" been glued to some basis board, or glass, or sth13:28
DocScrutinizerwell, maybe not. Think they cheated and just mirrored a picture "from the outside"13:29
DocScrutinizerotherwise you'd not see the white printing where copper is supposed to be seen "from inside"13:30
steve|mah well, they've done that just like me13:31
steve|mI started from both sides and just mirrored the other 3 layers in gimp13:31
steve|mwhich is totally awesome btw.. to match the layers after scanning, I adjust one via on the edge to match the other layer, and freely rotate the layer using that via as the center of the rotation13:33
DocScrutinizerI'd probably glue the board with "top silk" side to a thick glass plate, and take off layer by layer until only the white printing remains13:33
steve|mdon't know if that works out so well..13:34
steve|mbut would be worth a try13:34
DocScrutinizers/ stack that has either a lawn pixel with via tag or a copper pixel/ stack that has either a lawn pixel with via tag AND COPPER PIXEL NEXT TO VIA HOLE or a copper pixel/13:40
DocScrutinizer(actually you'd not need to tag via holes in trace layers, just filling occasional via holes in copper areas with copper should suffice. Make sure you don't detect via holes in lawn as via holes in copper though)13:42
DocScrutinizerI.E. you need a good distinction method to tell apart a hole from lawn on PCB13:44
DocScrutinizerso lawn isn't taken for a hole13:44
DocScrutinizerthen you safely can copper-fill holes in copper areas, while leaving alone holes in lawn areas13:45
DocScrutinizergiven all via holes are of same minuscule size and round shape shall ease that task13:47
DocScrutinizerdetection of via holes in via layers is more of a problem I guess13:48
DocScrutinizeryou probably could clog them easily with dust13:49
DocScrutinizerHAH, given the recursive nature of parent and child flood fill processes, you only need to check if (via)layer self-1 and/or self+1 have a hole. If yes: spawn child floodfill on next (trace)layer self+/-N that has copper in same position. Dont walk layer stack any further than that first layer with copper, child floodfill process will take care of that13:55
DocScrutinizerooops, of course child floodfill process mustn't walk back over the areas parent process already processed. You could take care of this by blocking child from walking layer stack in opposite direction for this one via13:57
DocScrutinizeror you actually fill traces with a new color that indicates "processed" and thus would stop child processes from walking back to origin automatically13:58
DocScrutinizeralso nice to watch on screen while it works, I guess :-D13:59
Action: DocScrutinizer wonders if you could easily implement all this as a gimp macro or plugin14:00
DocScrutinizerhmm, unknown format14:02
steve|mhm, plays fine here, even updated mimetypes to auto-play in firefox14:03
DocScrutinizermhm, FF. Lemme try14:04
steve|mVLC works fine as well14:04
DocScrutinizersorry, no codecs for this format14:05
steve|mthen you are on a totally outdated system :p14:05
DocScrutinizerwell, this PC is really poor on codecs14:06
steve|mthat's a webm container, 3mbit VP8 video encoded with libvpx, 128kbit audio with libvorbis14:07
steve|mbasically what youtube uses for their html5-beta14:07
DocScrutinizermhm, that doesn't work either here14:07
DocScrutinizermight try it on my phone, it has way better codecs (and also better GFX at alrge)14:08
steve|mseems like I should have used theora instead14:09
DocScrutinizermeh, "open with mediaplayer (extended media support)" -> download 12MB -> "media format not supported"14:11
steve|mwait a second..14:14
steve|mDocScrutinizer51: http://www.steve-m.de/files/pcb_lastlayer.ogv14:19
DocScrutinizer51let's see...14:20
DocScrutinizer51open in mediaplayer(ogg) :-)14:21
DocScrutinizershit, mediaplayer shows his special flavour equivalent of a sand-clock for ever14:25
DocScrutinizerkaffeine works :-D14:25
steve|mfirefox can play theora since version 3.1 natively14:25
DocScrutinizeron PC14:25
steve|mseems like there's still a long way down the road until flash-less webvideo arives everywhere :P14:26
DocScrutinizerMEH! kaffeine tries to stream, which fails due to my DSL not supporting the needed datarate, so the movie eventually blocks and doesn't restart. Need to download wnd play from local copy now :-/14:30
steve|mah well14:30
steve|mnext time I'll upload it on youtube I promise14:31
DocScrutinizernice video, thanks :-D14:37
Action: DocScrutinizer kicks N900 for not playing OGG14:38
Action: DocScrutinizer continues pondering idly over generic floodfill algorithms and realizes this is a nontrivial problem, esp for resource-optimized operation14:43
wpwrakbah, use a reasonably fine raster. memory and cpu cycles are very very cheap these days :)14:44
DocScrutinizerI envision a *huge* stack of points_yet_to_process14:44
wpwrakmore than 1 GB ? ;-)14:45
DocScrutinizerprolly not, though - who knows, when floodfilling a ground plane layer14:45
wpwrakthe number of points to process grows only with something like O(r*layers) where r is the radius from the origin14:46
DocScrutinizerreally not exactly trivial to do this in a optimized way, by any metrics14:46
wpwrakyou'll never find anything with even remotely the resolution for this number of points to become even the slightest problem. well, unless you insist on running it on a Ben maybe :)14:47
wpwrakalthough even the ben probably has enough memory for it. the actual images are more of an issue, with O(x*y*layers) memory14:48
DocScrutinizerprolly not, yet I just pondered a "run the border" algo, that aborts when crossing same pixel twice14:48
DocScrutinizerwouldn't probably need *any* stack14:48
wpwrakyou need one for the current periphery. plus you need a memory for which points you've already visited14:49
wpwrakbut all this is really quite simple. the hard bit is converting the image into a substrate/copper map14:49
DocScrutinizerlook around you, clockwise. Find first pixel of "victim" color that sits right of a "killed" pixel. Kill it. Jump on it. Restart. On error: jump to first pixel that is neither killed nor victim and right to a killed pixel. Restart14:51
wpwraki like the idea of using a cnc mill to shave off layers. shredding a board like this sound like lots of fun ;-)14:51
wpwrakfor these jumps, you either need a "to do" list or you have to search the bitmap every once in a while. not very efficient.14:52
wpwrak(the searching. the to do list is efficient)14:53
DocScrutinizerabort on crossing a non-killed-non-victim_pixel that you already been on before14:53
wpwrakyes yes, i know the algorithm. they've had it in c't some 20+ years ago ;-)14:54
DocScrutinizerfor the sake of easy handling of canvas borders: don't jump on a non-victim-non-killed pixel, but rather on the killed pixel left to it14:54
DocScrutinizerreally? in c't? So my memory inspired me to think I just invented that?14:55
wpwraknaw, add line line of substrate pixels as a border. then your algorithm will never try to leave the canvas14:55
wpwrakit's ANCIENT ;-)14:56
DocScrutinizerI bet it is14:56
DocScrutinizerI didn't *know* of it14:56
wpwrakit's an algorithm sometimes used for calculating traces (in a layout auto-route) in a grid-based context14:57
DocScrutinizerjust thought this would result exactly in a filling pattern I actually observe in painting programs14:57
wpwrakyes, it's the same concept14:57
wpwrakthe routing algorithm even finds the shortest path. if you don't need this, your storage requirement drops by O(log2 max_distance)14:58
DocScrutinizerI forgot what O() means14:58
wpwrakorder of. e.g., O(n^2) means that the algorithm will need approximately resources something+something*n^214:59
wpwrakfor n towards infinity, this then simply becomes something*n^215:00
DocScrutinizerindeed for routing it's ideal as it propagates equally in all directions (well actually only into x and y and maybe also diagonal)15:00
wpwraksee also http://en.wikipedia.org/wiki/Big_Oh_notation15:01
DocScrutinizerhmm, with diagonal moves it covers all directions :-)15:01
wpwrakand http://en.wikipedia.org/wiki/Analysis_of_algorithms15:01
wpwrakand if you have the stomach for it http://en.wikipedia.org/wiki/Computational_complexity15:02
wpwrakyou only need diagonals if your resolution is close to the structure width. otherwise (+1, +1) is simply (+1, 0) followed by (0, +1)15:03
DocScrutinizersure, but the distance is incorrect15:03
wpwrakdepends on your metric ;-) see also my recent posting about the logo (part 2, the keep out areas)15:04
DocScrutinizersomething on +X+Y has real distance sqrt(+X^2 + +Y^2) while this algo calculates distance as +X +  +Y15:05
wpwrakcorrect. the so-called manhattan distance15:06
DocScrutinizerwell, o it uses sqrt(X^2 + Y^2) :-P15:06
DocScrutinizerfor distance15:06
DocScrutinizerbut then it's not an implicit find of shortest anymore15:07
wpwrakif you're in a manhattan geometry it still does :)15:07
wpwrakit all depends on how you define the problem15:07
DocScrutinizerwell, here we got no problem related to distance. Just find all possible pathes15:08
wpwrakif you really want to screw with people's heads, use a hyperbolic n-space. euclid would get a big headache :)15:08
Action: DocScrutinizer too15:09
wpwrakyup, distance is just one bit :)15:09
DocScrutinizeryet I think it should be easy to augment gimp to do this PCB layer analysis job15:10
wpwrakoh dear ;-)15:10
wpwraki'd just write a few lines of C15:10
DocScrutinizera few?15:10
wpwrakwell, maybe a few hundred. it's not complicated.15:11
DocScrutinizerI'd write a few lines of C for a gimp plugin, exploiting gimp's handling of jpg, of layers, of canvas, of floodfill even15:11
wpwrakyou have N+2 types of points, derived from the images: substrate, copper, and pad(i)15:12
DocScrutinizeryeah - AFTER preprocessing the raw photos15:12
wpwrakthat's a completely separate processing strep15:12
DocScrutinizerwhich could be done in gimp as well15:13
wpwrakdenoise, maybe correct along gradients, etc.15:13
DocScrutinizera bit of object detection, at least for via holes15:14
wpwraksure. gimp has all the features you need.15:14
wpwrakso you care about via holes ? they're just copper, no ?15:14
wpwraksort of thin traces15:14
wpwrakif the same pixel in adjacent layers has copper, the two are connected15:15
DocScrutinizerhmm of course I care. Both for via planes that have holes and lawn on your original pictures. As well as for via holes in copper areas that need filling15:15
wpwraki don't see where the hole matters15:16
DocScrutinizercopper on via layers is rarely ever to be seen, it's too thin15:16
wpwrakthat would be a problem15:16
DocScrutinizerwhat you see though is the hole15:16
wpwrakokay, just treat hole like copper15:17
DocScrutinizerI don't assume a sub-pixel precision of the raw input data15:17
wpwraki would try to have as many pixels as possible. the more pixels, the easier to fish out the errors :)15:18
DocScrutinizerwpwrak: that's a good idea, and only needs a preprocessor step that actually does that filling of all holes with copper, on all layers15:18
DocScrutinizerall VIA holes15:18
DocScrutinizershouldn't fill larger holes though15:19
DocScrutinizer(as many pixel as possible) that's obvious15:19
wpwrakwhy not ? they're probably unconnected within the layers as well15:19
wpwrakotherwise, they may have accidental connections anyway15:20
wpwrake.g., if you have non-plated holes that just pinch through solid copper layers15:20
DocScrutinizerwhy not: because I'd assume a hole that's not the size and shape of a via is some error in raw data15:21
wpwrakcould be a through-hole component, a mounting hole, etc.15:21
wpwrakbut i don't think it matters. if it connects to copper horizontally, it probably is as good as a via :)15:22
DocScrutinizerbut could as well be a problem in via layer raw data. Via layer pictures are really noisy15:22
DocScrutinizerlook at "10: 2 <-> top vias" in http://en.qi-hardware.com/wiki/Sciphone_Dream_G2#PCB_layers15:23
wpwrakhmm, scratch marks15:25
wpwrakthe pictures are quite amazing indeed. just looked at them now.15:25
DocScrutinizerI tried http://en.qi-hardware.com/wiki/File:Sciphone_G2_PCB_10.png in gimp and played with "Swellwert anwenden" a bit15:30
DocScrutinizerI'd guess you for sure would want better pictures and still would see a benefit in shape recognition for the via holes15:31
DocScrutinizerdunno, maybe "unscharf maskieren" etc could also help15:31
DocScrutinizeremphasize small dust-alike structures, etc15:32
DocScrutinizersharpen edges15:33
larscDocScrutinizer: edge-detect15:38
DocScrutinizerwpwrak: see my prev comment >><DocScrutinizer> if you're curious about what's the deal with vias, a nice execise is to follow the TP018(?) marked "VBAT" in http://en.qi-hardware.com/wiki/Sciphone_Dream_G2#PCB_layers<< ff15:39
DocScrutinizeractually TP01715:39
DocScrutinizerlarsc: yep15:39
DocScrutinizerhmm shuld've used this: http://en.qi-hardware.com/w/images/e/e7/Sciphone_G2_PCB_10.png15:42
DocScrutinizerfor now I have no clue if the dim white somewhat larger round blobs are also vias, this time filled ones15:44
DocScrutinizerimpossible to tell without the original in front of me. If they are, we'd probably need better photos15:45
wanoxI would like to setup a irc bot similar to qi-bot, anyone can tell me how to?16:33
wanoxwatch git repository, when there is commit, send to channel16:33
kristianpaulwanox: there is a server setup page at en.qi-hardware.com/wiki16:59
wanoxkristianpaul: reading that, thanks17:11
lekernelwatching the video, those robots look pathetic compared to what e.g. boston dynamics does20:38
steve|m^ http://www.steve-m.de/projects/osmocom/bsp_sniffs/bsp_sniffing_setup.jpg21:23
steve|mah, damn21:23
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