| azonenberg | http://siliconpr0n.org/wiki/doku.php?id=classes:rpi_re | 14:09 |
|---|---|---|
| azonenberg | putting together a proposal to offer this class in the spring, any ideas? | 14:09 |
| Sync__ | pretty steep learning curve :D | 14:14 |
| azonenberg | You think it's too fast? What material would you spend >1 lecture on that is currently down as only 1? | 14:15 |
| Sync__ | well, going from no idea to extracting a schem in 5 weeks is pretty hard imho | 14:16 |
| azonenberg | Perhaps, but i need something more concrete | 14:16 |
| azonenberg | Is there material i should cover that i don't have there? | 14:16 |
| azonenberg | is there something i'm not spending enough time on? | 14:17 |
| Sync__ | how long are the lectures? | 14:17 |
| berndj | azonenberg, are you assuming that students would be familiar with the switch model for FETs? | 14:19 |
| azonenberg | berndj: Yes | 14:21 |
| berndj | depending on what knowledge / skill you assume, i think asking students to figure out what a cell does might be a bit hard so soon into the classes | 14:21 |
| azonenberg | Switch only, not assuming any knowledge of layout or analog characteristics | 14:21 |
| berndj | obviously also depends on the cell | 14:21 |
| azonenberg | the latter are beyond the scope of the class, and the former will be introduced | 14:21 |
| azonenberg | I'd do simple cells | 14:21 |
| azonenberg | like NAND4 or something | 14:21 |
| berndj | ok | 14:21 |
| azonenberg | then maybe a flipflop for extra credit | 14:22 |
| berndj | i was just thinking that some of the memory element cells could be a bit tough | 14:22 |
| azonenberg | oh, like a 6T SRAM? | 14:22 |
| azonenberg | Yeah, not going to do that so early in the course | 14:22 |
| berndj | how come SRAMs use 6 transistor cells but flipflops use loads more? | 14:23 |
| Sync__ | srams want to be fast | 14:24 |
| berndj | even that dynamic d-type flipflop is 9 | 14:24 |
| berndj | flipflops aren't supposed to be slow :-/ | 14:24 |
| azonenberg | SRAMs include array logic and they normally have differential inputs/outputs | 14:24 |
| azonenberg | the inverters etc don't count toward the 6 since you only include it at the edges of the array | 14:24 |
| berndj | ok that's a handful right there in the inverters | 14:25 |
| azonenberg | Yeah | 14:26 |
| azonenberg | but those arent in the cell | 14:26 |
| azonenberg | they're at the edges of the array | 14:26 |
| azonenberg | An N-bit SRAM array isn't 6N transistors | 14:26 |
| azonenberg | it's 6N + K*log(n) + M | 14:26 |
| azonenberg | for some constants K, M that depend on the array geometry etc | 14:27 |
| azonenberg | sorry, sqrt(n), not log(n) | 14:27 |
| --- Sat Nov 23 2013 | 00:00 | |
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