#homecmos IRC log for Tuesday, 2013-07-02

berndjare real-life multiplexers (as part of a bigger chip) purely combinational or do they play tricks with enabling/disabling one of the inputs onto a common bus?03:06
azonenbergberndj: i assume it varies03:13
azonenbergfor very wide muxes i'd imagine tristating is common03:14
azonenberg(as in lots of inputs, not many bits wide)03:14
berndjis 3-bits select (to select 1 from 8) "very wide"?03:14
azonenbergI'm not sure what the threshold is03:15
azonenbergall of the ones i do in FPGAs are purely combinatorial03:15
azonenbergbut thats because there aren't internal tristates03:15
berndji'm not really sure what the point to all this polygon doodling is but it feels educational03:16
azonenbergi'll be doing my share of that in six months or so03:16
azonenbergi'm planning to take vlsi in the spring03:16
berndjdo you get to make your very own cpu?03:17
azonenbergNo, that class mostly works at the cell level and below03:17
azonenbergadvanced computer hardware design aka ACHD works at the RTL level and i took already03:17
azonenbergthere's also one on designing standard cell ASICs that's rarely offered due to lack of faculty and demand from the student body03:18
berndjso yeah, i'm trying to decide between multiplexing one of 8 registers onto a logic pipeline, or whether to circulate those 8 registers in a ring and run the logic off a fixed tap03:18
berndj"standard cell ASICs" - does that imply there's such a thing as ASICs that don't use standard cells?03:19
azonenberganything analog :p03:22
berndji meant digital :)03:22
berndjthose 4004 masks looked pretty random to me, but maybe that's because non-cmos just is random like that - you don't need complementary logic the be adjacent (or anywhere)03:23
azonenbergthat's NMOS, and yeah03:24
azonenbergthat was also hand drawn03:24
azonenbergnot standard cells03:25
azonenbergor was it PMOS?03:25
azonenbergi forget03:25
azonenbergi know it was a single MOS family03:25
berndji vaguely recall PMOS for that early stuff03:27
berndjhow about this crazy idea: a pipeline of n-wide half adders, and keep circulating the carries back as addends until the carry vector is zero?20:42
berndjit looks like most 32-bit additions would complete in 4-6 cycles20:43
berndjSync_: i'm trying to come up with a power-efficient way of adding numbers20:44
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