| berndj | are real-life multiplexers (as part of a bigger chip) purely combinational or do they play tricks with enabling/disabling one of the inputs onto a common bus? | 03:06 |
|---|---|---|
| azonenberg | berndj: i assume it varies | 03:13 |
| azonenberg | for very wide muxes i'd imagine tristating is common | 03:14 |
| azonenberg | (as in lots of inputs, not many bits wide) | 03:14 |
| berndj | is 3-bits select (to select 1 from 8) "very wide"? | 03:14 |
| azonenberg | I'm not sure what the threshold is | 03:15 |
| azonenberg | all of the ones i do in FPGAs are purely combinatorial | 03:15 |
| azonenberg | but thats because there aren't internal tristates | 03:15 |
| berndj | i'm not really sure what the point to all this polygon doodling is but it feels educational | 03:16 |
| azonenberg | lol | 03:16 |
| azonenberg | i'll be doing my share of that in six months or so | 03:16 |
| azonenberg | i'm planning to take vlsi in the spring | 03:16 |
| berndj | do you get to make your very own cpu? | 03:17 |
| azonenberg | No, that class mostly works at the cell level and below | 03:17 |
| azonenberg | advanced computer hardware design aka ACHD works at the RTL level and i took already | 03:17 |
| azonenberg | there's also one on designing standard cell ASICs that's rarely offered due to lack of faculty and demand from the student body | 03:18 |
| berndj | so yeah, i'm trying to decide between multiplexing one of 8 registers onto a logic pipeline, or whether to circulate those 8 registers in a ring and run the logic off a fixed tap | 03:18 |
| berndj | "standard cell ASICs" - does that imply there's such a thing as ASICs that don't use standard cells? | 03:19 |
| azonenberg | Sure | 03:22 |
| azonenberg | anything analog :p | 03:22 |
| berndj | i meant digital :) | 03:22 |
| berndj | those 4004 masks looked pretty random to me, but maybe that's because non-cmos just is random like that - you don't need complementary logic the be adjacent (or anywhere) | 03:23 |
| azonenberg | that's NMOS, and yeah | 03:24 |
| azonenberg | that was also hand drawn | 03:24 |
| azonenberg | not standard cells | 03:25 |
| azonenberg | or was it PMOS? | 03:25 |
| azonenberg | i forget | 03:25 |
| azonenberg | i know it was a single MOS family | 03:25 |
| berndj | i vaguely recall PMOS for that early stuff | 03:27 |
| berndj | how about this crazy idea: a pipeline of n-wide half adders, and keep circulating the carries back as addends until the carry vector is zero? | 20:42 |
| Sync_ | wat | 20:43 |
| berndj | it looks like most 32-bit additions would complete in 4-6 cycles | 20:43 |
| berndj | Sync_: i'm trying to come up with a power-efficient way of adding numbers | 20:44 |
| --- Wed Jul 3 2013 | 00:00 | |
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