| --- Sat Jun 29 2013 | 00:00 | |
| berndj | magic's drc complains when a substrate contact is less than 4 lambda from a diffusion contact, also that opposite diffusions are too close | 18:08 |
|---|---|---|
| berndj | but when i put the substrate contact directly adjacent to the diffusion contact, drc is happy. what gives? why is "opposite diffusions too close" not a problem then? | 18:08 |
| berndj | in both cases the intent is to strap the contacts together with m1. is it that magic's drc can't "see" that the contacts are strapped together, when there's a short m1 jumper connecting them? | 18:09 |
| azonenberg | Probably | 19:35 |
| berndj | whee, the dff simulates correctly! | 19:48 |
| berndj | not a full spice sim, just irsim's switch model simulation | 19:49 |
| azonenberg | :D | 19:50 |
| azonenberg | On a somewhat related note | 19:50 |
| berndj | http://www.bpj-code.co.za/downloads/btc-miner/dff-sim.png with "final" layout http://www.bpj-code.co.za/downloads/btc-miner/dff.png | 19:50 |
| azonenberg | i want to make a tool for automatic recognition of standard cells at some point | 19:50 |
| azonenberg | In other words, given optical or secondary electron images of each layer | 19:51 |
| berndj | that sounds hard :-/ | 19:51 |
| azonenberg | generate vectors | 19:51 |
| azonenberg | (possibly after manually drawing the boundary of each cell) | 19:51 |
| azonenberg | then extract transistors from the vector images | 19:51 |
| azonenberg | and so a behavioral (not necessarily SPICE-level since process details are unknown) simulation with all possible inputs | 19:51 |
| azonenberg | and maybe some heuristics to speed things up | 19:51 |
| azonenberg | to determine "this is a NAND3" | 19:51 |
| azonenberg | "this is a positive edge triggered dff" | 19:52 |
| berndj | that last step is the one i don't even know how i don't know how to do it | 19:52 |
| azonenberg | Yeah | 19:52 |
| azonenberg | Basically, right now the first step in REing a standard cell chip is manually figuring out what each cell does | 19:52 |
| azonenberg | i'd like to automate that | 19:52 |
| Sync_ | yeah that's a good idea ;) | 19:53 |
| azonenberg | say "this is a cell", highlight it | 19:53 |
| azonenberg | five seconds later "NAND2x1" | 19:53 |
| berndj | would it be useful if you could at least find instances of common cells, regardless of their function? | 19:53 |
| azonenberg | degate can find cells once you higlight one instance and give it a name | 19:53 |
| berndj | "there's a cell here, and it's the same as the one here, here and here" | 19:53 |
| azonenberg | But it can't tell what is a cell | 19:53 |
| azonenberg | That would be a little harder but nice | 19:53 |
| Sync_ | oh degate can do that now | 19:53 |
| Sync_ | cool | 19:53 |
| azonenberg | Degate also segfaults | 19:54 |
| Sync_ | yes it is good at that | 19:54 |
| azonenberg | whenever i try to add >1 layer in the last version i tried | 19:54 |
| azonenberg | i'm leaning toward writing my own tool | 19:54 |
| azonenberg | its too unstable :p | 19:54 |
| Sync_ | yeah it sucks | 19:56 |
| azonenberg | What I dream of is an IDA for hardware | 19:56 |
| azonenberg | something that takes in either an FPGA bitstream or die photos | 19:56 |
| azonenberg | does extractions and recognizes cells on the photos, reverses the bitstream | 19:57 |
| azonenberg | now you have a cell-level netlist | 19:57 |
| azonenberg | then do heuristics and isomorphism checking within neighborhoods to find higher level structures like adders and muxes | 19:57 |
| azonenberg | and perhaps even known hard IP blocks | 19:57 |
| berndj | hash it all and make a rainbow table! | 19:58 |
| Sync_ | oh actually, have y | 19:58 |
| Sync_ | gah | 19:58 |
| Sync_ | wrong channel | 19:58 |
| azonenberg | berndj: lol | 19:59 |
| azonenberg | seriousl, it would be awesome to take in die images and have it automatically find "functions" like ida does | 20:00 |
| azonenberg | but they're standard cells | 20:00 |
| azonenberg | then find higher level structures | 20:00 |
| azonenberg | and "decompile" the result to generic RTL | 20:00 |
| azonenberg | one module at first, you could then split stuff off as you saw fit | 20:00 |
| Sync_ | I wonder when chip manufacturers will start to implement measures to stop people FIB from the bottom of the die | 20:01 |
| azonenberg | well 3D stuff is going to be a big PITA to reverse :p | 20:03 |
| Sync_ | yeah but that's not too popular :P | 20:08 |
| Sync_ | having annoying structures on top is | 20:08 |
| Sync_ | and I finally made some progress in metalization | 20:09 |
| berndj | what's #D stuff going to do to power densities? | 20:13 |
| berndj | aargh shift key! i mean 3D stuff | 20:14 |
| --- Sun Jun 30 2013 | 00:00 | |
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