| azonenberg | berndj: Probably lol | 00:38 |
|---|---|---|
| azonenberg | i think you end up getting the isolation diodes forward biased all the time :p | 00:38 |
| azonenberg | Unless i'm misunderstanding the question | 00:38 |
| berndj | azonenberg: no, i'd flip *everything*, including the well contacts | 00:39 |
| azonenberg | oh... hmm | 00:40 |
| berndj | i'd probably make the inverted section narrower than the rest of the cell, so the power rails could still go straight across, but a "private" rail for the inverted rails | 00:40 |
| azonenberg | hmm, sounds overcomplicated | 00:40 |
| azonenberg | maybe cheat and use poly as a routing layer? :p | 00:41 |
| azonenberg | Though you can't do that on a modern process | 00:41 |
| azonenberg | they usually do double patterning etc on poly | 00:41 |
| berndj | i wanted to try laying out that dff like that to see if it saves real estate compared to using jumpers to get gate signals to cross over each other | 00:41 |
| azonenberg | i see | 00:41 |
| azonenberg | What process node are you targeting? | 00:41 |
| berndj | magic calls it "scalable cmos" | 00:42 |
| azonenberg | So presumably relatively large? | 00:42 |
| berndj | but it's more polygon doodling and self-didactic than actually making something real | 00:42 |
| azonenberg | like 180nm or so? | 00:42 |
| berndj | probably | 00:42 |
| azonenberg | you can get away with lots of stuff at those levels that you could never do at 22nm | 00:42 |
| berndj | are you saying the design rules are overrestrictive considering modern processes? | 00:43 |
| berndj | i mean that, if you used a 22nm process to build a 180nm chip, you'd have the luxury of using 22nm rules, not the 180nm rules | 00:44 |
| azonenberg | luxury, lol | 00:44 |
| azonenberg | no | 00:44 |
| azonenberg | it probably wouldnt even pass DRC | 00:44 |
| berndj | but i thought the big processes were actually just all the old equipment, hence old rules | 00:44 |
| azonenberg | What i mean is, it's generally not possible to build a chip five gens old on a modern porcess | 00:44 |
| azonenberg | process* | 00:44 |
| berndj | *not possible*? | 00:45 |
| azonenberg | maybe if you retooled the masks or the process workflow a lot | 00:45 |
| azonenberg | TSMC 28nm for example uses double patterning | 00:45 |
| berndj | oh, you mean the same chip 5 times smaller? | 00:45 |
| azonenberg | http://1.bp.blogspot.com/-USbzZsa8_BU/ThvYKRgGlTI/AAAAAAAAAI4/-g0gIaDX0A0/s1600/Kintex2.jpg | 00:45 |
| azonenberg | No, i mean the same size | 00:45 |
| azonenberg | This is from a Kintex-7 FPGA | 00:45 |
| azonenberg | Note that the gates are all exactly the same size and regularly spaced | 00:45 |
| azonenberg | The process cannot make a gate any bigger or smaller | 00:46 |
| azonenberg | (you're looking at poly and active) | 00:46 |
| azonenberg | TSMC 28nm | 00:46 |
| azonenberg | It's two litho steps, one for defining the parallel lines and then one for cutting them vertically | 00:46 |
| azonenberg | It wouldn't surprise me if the parallel lines are generated by some kind of interference pattern | 00:47 |
| berndj | i thought that's what "double patterning" is? | 00:47 |
| berndj | (interference magic) | 00:47 |
| azonenberg | Not strictly | 00:47 |
| azonenberg | There's a half dozen or soe forms of double patterning | 00:47 |
| azonenberg | I dont know exactly what they used here | 00:47 |
| azonenberg | Its possible this is actually triple litho | 00:47 |
| azonenberg | one double-patterning step for the lnies, then another for the cut | 00:48 |
| azonenberg | another single litho* | 00:48 |
| azonenberg | Anyway the point is, larger processes are generally less restrictive in terms of allowing arbitrary geometry that doesn't violate clearance or density rules | 00:48 |
| azonenberg | For example if you are not using copper damascene or CMP, you don't need fill patterns or uniform metal density | 00:49 |
| berndj | what's that about btw - not setting up unequal thermal stresses? | 00:50 |
| azonenberg | No | 00:50 |
| azonenberg | The problem is that copper and oxide polish at different rates | 00:50 |
| azonenberg | and you dont want sagging (since the pad isn't perfectly flat, it'll deform slightly if one area polishes faster than another and make the problem worse) | 00:51 |
| azonenberg | So you want uniform, roughly, metal density | 00:51 |
| berndj | interesting | 00:51 |
| berndj | so many weird things that happen | 00:51 |
| berndj | also: those power rails on micrographs have a continuous row of contacts; is this important or would it be (electrically) enough to have one or two contacts into a mini-well that's "wrong way round"? | 01:04 |
| azonenberg | Not sure if you need that many | 01:10 |
| berndj | hmm, so you can only have one width of poly in some processes? | 01:50 |
| azonenberg | Yeah | 01:59 |
| azonenberg | And it has to be axially aligned | 01:59 |
| azonenberg | and exactly the same size | 01:59 |
| azonenberg | pretty much uniform pattern | 01:59 |
| azonenberg | i'm not sure how much you're able to deviate from that | 01:59 |
| berndj | so no non-manhattan lines either? | 02:03 |
| azonenberg | Older chips did 45deg but i rarely if ever see them in modern devices | 02:03 |
| azonenberg | except in really large geometry like power buses | 02:03 |
| azonenberg | that may just be due to the autorouters though | 02:03 |
| berndj | i think i've done it | 02:20 |
| berndj | almost. i just have to squeeze in an m2 contact here | 02:23 |
| berndj | magic's drc won't let me put it on top of a poly contact though :( | 02:23 |
| berndj | "via must be on a flat surface" which is fair enough i guess | 02:24 |
| berndj | http://www.bpj-code.co.za/downloads/btc-miner/dff.png | 02:50 |
| berndj | meh, i just realized i didn't make well contacts under the main power rails | 02:50 |
| berndj | it's supposed to implement the schematic (sans w/l ratios) at http://vlsitechnology.org/html/cells/wsclib013/dfnt1.html btw | 03:02 |
| --- Thu Jun 27 2013 | 00:00 | |
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