#homecmos IRC log for Wednesday, 2013-06-26

azonenbergberndj: Probably lol00:38
azonenbergi think you end up getting the isolation diodes forward biased all the time :p00:38
azonenbergUnless i'm misunderstanding the question00:38
berndjazonenberg: no, i'd flip *everything*, including the well contacts00:39
azonenbergoh... hmm00:40
berndji'd probably make the inverted section narrower than the rest of the cell, so the power rails could still go straight across, but a "private" rail for the inverted rails00:40
azonenberghmm, sounds overcomplicated00:40
azonenbergmaybe cheat and use poly as a routing layer? :p00:41
azonenbergThough you can't do that on a modern process00:41
azonenbergthey usually do double patterning  etc on poly00:41
berndji wanted to try laying out that dff like that to see if it saves real estate compared to using jumpers to get gate signals to cross over each other00:41
azonenbergi see00:41
azonenbergWhat process node are you targeting?00:41
berndjmagic calls it "scalable cmos"00:42
azonenbergSo presumably relatively large?00:42
berndjbut it's more polygon doodling and self-didactic than actually making something real00:42
azonenberglike 180nm or so?00:42
berndjprobably00:42
azonenbergyou can get away with lots of stuff at those levels that you could never do at 22nm00:42
berndjare you saying the design rules are overrestrictive considering modern processes?00:43
berndji mean that, if you used a 22nm process to build a 180nm chip, you'd have the luxury of using 22nm rules, not the 180nm rules00:44
azonenbergluxury, lol00:44
azonenbergno00:44
azonenbergit probably wouldnt even pass DRC00:44
berndjbut i thought the big processes were actually just all the old equipment, hence old rules00:44
azonenbergWhat i mean is, it's generally not possible to build a chip five gens old on a modern porcess00:44
azonenbergprocess*00:44
berndj*not possible*?00:45
azonenbergmaybe if you retooled the masks or the process workflow a lot00:45
azonenbergTSMC 28nm for example uses double patterning00:45
berndjoh, you mean the same chip 5 times smaller?00:45
azonenberghttp://1.bp.blogspot.com/-USbzZsa8_BU/ThvYKRgGlTI/AAAAAAAAAI4/-g0gIaDX0A0/s1600/Kintex2.jpg00:45
azonenbergNo, i mean the same size00:45
azonenbergThis is from a Kintex-7 FPGA00:45
azonenbergNote that the gates are all exactly the same size and regularly spaced00:45
azonenbergThe process cannot make a gate any bigger or smaller00:46
azonenberg(you're looking at poly and active)00:46
azonenbergTSMC 28nm00:46
azonenbergIt's two litho steps, one for defining the parallel lines and then one for cutting them vertically00:46
azonenbergIt wouldn't surprise me if the parallel lines are generated by some kind of interference pattern00:47
berndji thought that's what "double patterning" is?00:47
berndj(interference magic)00:47
azonenbergNot strictly00:47
azonenbergThere's a half dozen or soe forms of double patterning00:47
azonenbergI dont know exactly what they used here00:47
azonenbergIts possible this is actually triple litho00:47
azonenbergone double-patterning step for the lnies, then another for the cut00:48
azonenberganother single litho*00:48
azonenbergAnyway the point is, larger processes are generally less restrictive in terms of allowing arbitrary geometry that doesn't violate clearance or density rules00:48
azonenbergFor example if you are not using copper damascene or CMP, you don't need fill patterns or uniform metal density00:49
berndjwhat's that about btw - not setting up unequal thermal stresses?00:50
azonenbergNo00:50
azonenbergThe problem is that copper and oxide polish at different rates00:50
azonenbergand you dont want sagging (since the pad isn't perfectly flat, it'll deform slightly if one area polishes faster than another and make the problem worse)00:51
azonenbergSo you want uniform, roughly, metal density00:51
berndjinteresting00:51
berndjso many weird things that happen00:51
berndjalso: those power rails on micrographs have a continuous row of contacts; is this important or would it be (electrically) enough to have one or two contacts into a mini-well that's "wrong way round"?01:04
azonenbergNot sure if you need that many01:10
berndjhmm, so you can only have one width of poly in some processes?01:50
azonenbergYeah01:59
azonenbergAnd it has to be axially aligned01:59
azonenbergand exactly the same size01:59
azonenbergpretty much uniform pattern01:59
azonenbergi'm not sure how much you're able to deviate from that01:59
berndjso no non-manhattan lines either?02:03
azonenbergOlder chips did 45deg but i rarely if ever see them in modern devices02:03
azonenbergexcept in really large geometry like power buses02:03
azonenbergthat may just be due to the autorouters though02:03
berndji think i've done it02:20
berndjalmost. i just have to squeeze in an m2 contact here02:23
berndjmagic's drc won't let me put it on top of a poly contact though :(02:23
berndj"via must be on a flat surface" which is fair enough i guess02:24
berndjhttp://www.bpj-code.co.za/downloads/btc-miner/dff.png02:50
berndjmeh, i just realized i didn't make well contacts under the main power rails02:50
berndjit's supposed to implement the schematic (sans w/l ratios) at http://vlsitechnology.org/html/cells/wsclib013/dfnt1.html btw03:02
--- Thu Jun 27 201300:00

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