| berndj | ooh i think i get it, that latch uses the clock to select whether it's a 2-inverter cycle or a 2-inverter buffer of the input ref: http://uvicrec.blogspot.com/2012/03/sidoku-1.html | 00:36 |
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| berndj | is it generally "who cares?" regarding crossover currents during the clock transition? (the negated clock being slightly behind the positive clock, leaving both the output and the input trying to drive the internal "memory" node) | 00:39 |
| berndj | i'm probably just being too stingy with real estate with this layout | 02:08 |
| azonenberg | lol | 02:15 |
| azonenberg | I think it's best to try to buffer them both to the same approximate phase | 02:15 |
| azonenberg | But that may not always be done | 02:15 |
| Sync_ | berndj: you should get it as close as possible but for low frequencies it doesn't matter a lot | 08:59 |
| berndj | i was just wondering about that crowbar current issue while looking at that latch where the one transfer gate will be slightly behind the other; clearly it's "who cares?" in that case | 19:04 |
| --- Thu Jun 20 2013 | 00:00 | |
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