#homecmos IRC log for Wednesday, 2013-06-19

berndjooh i think i get it, that latch uses the clock to select whether it's a 2-inverter cycle or a 2-inverter buffer of the input ref: http://uvicrec.blogspot.com/2012/03/sidoku-1.html00:36
berndjis it generally "who cares?" regarding crossover currents during the clock transition? (the negated clock being slightly behind the positive clock, leaving both the output and the input trying to drive the internal "memory" node)00:39
berndji'm probably just being too stingy with real estate with this layout02:08
azonenbergI think it's best to try to buffer them both to the same approximate phase02:15
azonenbergBut that may not always be done02:15
Sync_berndj: you should get it as close as possible but for low frequencies it doesn't matter a lot08:59
berndji was just wondering about that crowbar current issue while looking at that latch where the one transfer gate will be slightly behind the other; clearly it's "who cares?" in that case19:04
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