| --- Sat May 25 2013 | 00:00 | |
| berndj | azonenberg: what limits the clock speed of those things with slicex/slicel/slicem? | 13:11 |
|---|---|---|
| azonenberg | berndj: you mean spartan-6? or FPGAs in general? | 22:25 |
| azonenberg | In any sequential/clocked logic | 22:25 |
| berndj | i guess spartan-6 | 22:25 |
| azonenberg | there are two possible limitations to maximum operating frequency | 22:25 |
| berndj | trying to compare apples with apples, not with oranges :) | 22:25 |
| azonenberg | the first is how fast you can clock individual elements (flipflops, RAM blocks, etc) | 22:25 |
| azonenberg | The second is propagation delay | 22:26 |
| azonenberg | you cannot send the second clock signal to a flipflop until the data generated by the previous one has arrived | 22:26 |
| azonenberg | This can be further subdivided into switching delay of logic elements and routing delay on wires | 22:26 |
| berndj | i was reading about that fpga miner (bitcoin stuff) that could go up to about 135MHz - is that likely the first or the second constraint? | 22:26 |
| azonenberg | in FPGAs, routing delay tends to dominate | 22:26 |
| azonenberg | Oh, sorry | 22:26 |
| azonenberg | there's a third constraint | 22:26 |
| azonenberg | Power | 22:26 |
| azonenberg | The faster you switch the more power you need | 22:27 |
| Sync_ | yes I have found out the hard way that ignoring the design softwares ideas can lead to interesting behavior | 22:27 |
| azonenberg | at some point you reach a situation in which you either cannot sink the heat fast enough, or you cannot feed electricity in fast enough | 22:27 |
| azonenberg | In general, propagation delay is your limiting factor for most logic | 22:27 |
| azonenberg | Extremely deeply pipelined stuff may run into the other two | 22:27 |
| berndj | yeah; is the power limit something that applies over the whole chip, or can you have (and feel) local intra-chip constraints? | 22:27 |
| azonenberg | in large chips, there can indeed be power limits for subregions | 22:28 |
| azonenberg | Anyway, in FPGAs normally you have a hard time operating THAT fast | 22:28 |
| azonenberg | because propagation delays dominate | 22:28 |
| azonenberg | Generally the logic elements are pretty fast | 22:28 |
| azonenberg | and the wires are slow | 22:28 |
| azonenberg | because you not only have R/C and transmission line delay | 22:28 |
| azonenberg | you also have switching delay for the multiplexers every time you change direction etc | 22:28 |
| berndj | so does 135MHz smell like routing delay or like element clocking? | 22:29 |
| azonenberg | Definitely routing delay | 22:29 |
| azonenberg | most block ram, DSP slices, etc in s6 can run up to 300-500 MHz if you can feed it data fast enough | 22:29 |
| berndj | what sort of numbers would you see if it were clocking or power limits? | 22:29 |
| azonenberg | The global clock tree, for example, cannot go over 500 | 22:30 |
| berndj | there's an internal clock synthesizer, right? | 22:30 |
| azonenberg | There are PLLs, yes | 22:30 |
| azonenberg | but you need an external oscillator | 22:30 |
| berndj | or do you actually have to feed in 500MHz if you want that | 22:30 |
| azonenberg | You need an external clock which can be multiplied or divided by the PLL | 22:30 |
| azonenberg | but it needs something to lock onto | 22:31 |
| azonenberg | Usually I have a 20-100 MHz external clock | 22:31 |
| azonenberg | multiply up to around a GHz on the PLL so i have lots of common factors | 22:31 |
| azonenberg | then divide down to whatever i actually need | 22:31 |
| azonenberg | on spartan6 the PLL's internal VCO frequency has to be in the 480-1080 MHz range iirc | 22:31 |
| azonenberg | So if you want to turn, say, 20 into 40 | 22:31 |
| azonenberg | you could multiply the 20 by 32 (the max allowed multiplier) up to 640 and then divide by 16 to get 40 | 22:32 |
| azonenberg | Anyway, typical values for delays on spartan6 are about 30% gate/logic delay and 70% routing delay | 22:32 |
| berndj | so i was just doing some exploratory design research for how to do a 74-series miner. it'd be 100+ chips just to make a very slow (20kH/s) miner | 22:48 |
| --- Sun May 26 2013 | 00:00 | |
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