#homecmos IRC log for Saturday, 2013-05-25

--- Sat May 25 201300:00
berndjazonenberg: what limits the clock speed of those things with slicex/slicel/slicem?13:11
azonenbergberndj: you mean spartan-6? or FPGAs in general?22:25
azonenbergIn any sequential/clocked logic22:25
berndji guess spartan-622:25
azonenbergthere are two possible limitations to maximum operating frequency22:25
berndjtrying to compare apples with apples, not with oranges :)22:25
azonenbergthe first is how fast you can clock individual elements (flipflops, RAM blocks, etc)22:25
azonenbergThe second is propagation delay22:26
azonenbergyou cannot send the second clock signal to a flipflop until the data generated by the previous one has arrived22:26
azonenbergThis can be further subdivided into switching delay of logic elements and routing delay on wires22:26
berndji was reading about that fpga miner (bitcoin stuff) that could go up to about 135MHz - is that likely the first or the second constraint?22:26
azonenbergin FPGAs, routing delay tends to dominate22:26
azonenbergOh, sorry22:26
azonenbergthere's a third constraint22:26
azonenbergThe faster you switch the more power you need22:27
Sync_yes I have found out the hard way that ignoring the design softwares ideas can lead to interesting behavior22:27
azonenbergat some point you reach a situation in which you either cannot sink the heat fast enough, or you cannot feed electricity in fast enough22:27
azonenbergIn general, propagation delay is your limiting factor for most logic22:27
azonenbergExtremely deeply pipelined stuff may run into the other two22:27
berndjyeah; is the power limit something that applies over the whole chip, or can you have (and feel) local intra-chip constraints?22:27
azonenbergin large chips, there can indeed be power limits for subregions22:28
azonenbergAnyway, in FPGAs normally you have a hard time operating THAT fast22:28
azonenbergbecause propagation delays dominate22:28
azonenbergGenerally the logic elements are pretty fast22:28
azonenbergand the wires are slow22:28
azonenbergbecause you not only have R/C and transmission line delay22:28
azonenbergyou also have switching delay for the multiplexers every time you change direction etc22:28
berndjso does 135MHz smell like routing delay or like element clocking?22:29
azonenbergDefinitely routing delay22:29
azonenbergmost block ram, DSP slices, etc in s6 can run up to 300-500 MHz if you can feed it data fast enough22:29
berndjwhat sort of numbers would you see if it were clocking or power limits?22:29
azonenbergThe global clock tree, for example, cannot go over 50022:30
berndjthere's an internal clock synthesizer, right?22:30
azonenbergThere are PLLs, yes22:30
azonenbergbut you need an external oscillator22:30
berndjor do you actually have to feed in 500MHz if you want that22:30
azonenbergYou need an external clock which can be multiplied or divided by the PLL22:30
azonenbergbut it needs something to lock onto22:31
azonenbergUsually I have a 20-100 MHz external clock22:31
azonenbergmultiply up to around a GHz on the PLL so i have lots of common factors22:31
azonenbergthen divide down to whatever i actually need22:31
azonenbergon spartan6 the PLL's internal VCO frequency has to be in the 480-1080 MHz range iirc22:31
azonenbergSo if you want to turn, say, 20 into 4022:31
azonenbergyou could multiply the 20 by 32 (the max allowed multiplier) up to 640 and then divide by 16 to get 4022:32
azonenbergAnyway, typical values for delays on spartan6 are about 30% gate/logic delay and 70% routing delay22:32
berndjso i was just doing some exploratory design research for how to do a 74-series miner. it'd be 100+ chips just to make a very slow (20kH/s) miner22:48
--- Sun May 26 201300:00

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