| --- Sun Dec 16 2012 | 00:00 | |
| kristianpaul | azonenberg: http://www.bunniestudios.com/blog/?p=2686 | 04:53 |
|---|---|---|
| azonenberg | Saw it already | 04:53 |
| azonenberg | Looks interesting | 04:54 |
| wolfspra1l | azonenberg: I'm looking a bit into hls (high-level synthesis) now | 05:15 |
| wolfspra1l | panda, shang, legup, c-to-verilog, fpgac, etc. | 05:15 |
| azonenberg | cool | 05:15 |
| wolfspra1l | do you know much about that? | 05:15 |
| azonenberg | No | 05:15 |
| wolfspra1l | I am wondering whether I should work on a llvm-backend for fpgatools | 05:15 |
| azonenberg | You might want to look at xc2c* at some point | 05:15 |
| wolfspra1l | what is that? | 05:15 |
| azonenberg | coolrunner-ii CPLDs | 05:15 |
| azonenberg | the bitstream for the smallest device is only ~12kbits | 05:15 |
| azonenberg | programming files are ASCII and even include comments | 05:16 |
| azonenberg | for which bits go to which function block etc | 05:16 |
| wolfspra1l | I don't know anything about those chips | 05:16 |
| wolfspra1l | why would I want to look at them? | 05:16 |
| azonenberg | they're CPLDs so the microarchitecture is totally different from FPGAs | 05:16 |
| azonenberg | but they're dirt cheap (like a dollar a pop) | 05:16 |
| azonenberg | and very simple | 05:16 |
| azonenberg | a full toolchain would likely take a lot less time than something like xc6s | 05:17 |
| azonenberg | But the downside is that since the uarch is so different from fpgas not much would port | 05:17 |
| wolfspra1l | why would I want to look at them? | 05:17 |
| azonenberg | Because they're probably the easiest programmable logic in current production to make a full FOSS toolchain for | 05:18 |
| wolfspra1l | I know nothing about those chips so maybe it's good to learn, but I wouldn't know why right now | 05:18 |
| azonenberg | not useful for much more than glue logic etc, of course | 05:18 |
| azonenberg | few hundred to few thousand gate equivalents | 05:18 |
| wolfspra1l | then you go and try :-) | 05:18 |
| wolfspra1l | what I see in xc6 so far is all very easy | 05:18 |
| azonenberg | there's a reason i mentioned you should look ;) | 05:18 |
| wolfspra1l | but what is better about those chips than say xc6slx9 ? | 05:19 |
| azonenberg | i'm looking into them in more depth though | 05:19 |
| wolfspra1l | my current toy | 05:19 |
| azonenberg | Oh, xc6s would be much better to have a full toolchain for in the long term | 05:19 |
| wolfspra1l | put the 'ease to write foss toolchain' aside for a moment | 05:19 |
| wolfspra1l | ah ok | 05:19 |
| wolfspra1l | then I shall continue there :-) | 05:19 |
| azonenberg | but i think as a short-term goal if you want a FOSS programmable logic toolchain for ANYTHING | 05:19 |
| azonenberg | those would be the quickest route | 05:19 |
| wolfspra1l | has someone tried? | 05:19 |
| azonenberg | Not to my knowledge | 05:20 |
| azonenberg | I might look at that since there would be little overlap with fpgatools | 05:20 |
| azonenberg | the microarchitecture has basically nothign in common | 05:20 |
| azonenberg | but it's extremely simple | 05:20 |
| wolfspra1l | sure | 05:20 |
| azonenberg | just a bunch of muxes and sum-of-products arrays | 05:20 |
| wolfspra1l | I like to first understand the quality of the chip (the hw) | 05:20 |
| wolfspra1l | let's assume all sw can be written | 05:20 |
| azonenberg | Yeah | 05:20 |
| azonenberg | Thats the thing that makes these attractive targets for study - simplicity | 05:20 |
| azonenberg | a couple of global clocks and stuff | 05:20 |
| wolfspra1l | if by that comparison there is nothing or not much interesting left in xc2c*, then I'm probably not interested | 05:20 |
| azonenberg | IOBs | 05:20 |
| azonenberg | then just logic | 05:20 |
| azonenberg | no multipliers, no ram, no SERDES, no memory controller | 05:21 |
| wolfspra1l | again: I have done a lot of work on xc6 in the last months | 05:21 |
| azonenberg | Yeah | 05:21 |
| wolfspra1l | and I tell you: it's all easy | 05:21 |
| azonenberg | Given where you are, you should keep going | 05:21 |
| azonenberg | i'll look at xc2c over the winter break if i have time | 05:21 |
| wolfspra1l | I will have the blinking led finished this coming week | 05:21 |
| azonenberg | :D | 05:21 |
| wolfspra1l | then a counter with bscan-accessible register | 05:21 |
| wolfspra1l | then probably some experiments with that small j1 core/soc | 05:21 |
| wolfspra1l | bram | 05:22 |
| azonenberg | also i have (mostly) open source code working now for downloading bitstreams over jtag | 05:22 |
| wolfspra1l | and finally I need an efficient way to program the thing, so I look into hls now | 05:22 |
| azonenberg | no xilinx tools needed | 05:22 |
| azonenberg | mostly open as in my code is bsd licensed but depends on an API that is, i think, not truly FOSS | 05:22 |
| wolfspra1l | sure, me too - it's included with fpgatools in the mini-jtag subdir | 05:22 |
| azonenberg | at least the Digilent API is not | 05:22 |
| azonenberg | i need to look into the FTDI api | 05:22 |
| azonenberg | is libftdi open? | 05:22 |
| wolfspra1l | can you look at mini-jtag ? maybe there is something I can adopt from your stuff or merge? | 05:23 |
| azonenberg | I'll look soon | 05:23 |
| azonenberg | My code isnt measnt for programming, though it has that capability | 05:23 |
| azonenberg | the main point is a debug bridge for my SoC bus | 05:23 |
| wolfspra1l | so hls? never tried? | 05:23 |
| azonenberg | Yeah, no experience with it | 05:23 |
| wolfspra1l | you don't know these panda/shang/legup thingies? | 05:24 |
| wolfspra1l | ok | 05:24 |
| wolfspra1l | azonenberg: any other news? | 05:31 |
| wolfspra1l | how about the slx9 pics? :-) | 05:31 |
| wolfspra1l | on my side just moving forward nicely, slow though | 05:31 |
| azonenberg | wolfspra1l: the tungsten SEM on campus probably lacks the necessary resolutoin | 05:32 |
| azonenberg | i need to get trained on the FESEM | 05:32 |
| azonenberg | which happens soon | 05:32 |
| azonenberg | i also need to get the chip decapped, havent had time to do that either | 05:32 |
| wolfspra1l | nice | 05:32 |
| azonenberg | i have one last stack of homework to grade and then i'm done for the semester | 05:32 |
| wolfspra1l | I can't be that far off from finally having something that resembles a 'programmable' chip | 05:33 |
| azonenberg | nice | 05:33 |
| wolfspra1l | though it will require months more of work | 05:33 |
| wolfspra1l | but the pieces are coming together and it all works well | 05:33 |
| wolfspra1l | currently trying to finish the blinking led | 05:34 |
| wolfspra1l | which includes clock routing, more logic features than before | 05:34 |
| azonenberg | nice | 05:34 |
| wolfspra1l | thinking about the coolrunners again | 05:38 |
| wolfspra1l | make the pitch - why are those chips good? | 05:38 |
| wolfspra1l | cheap, ok | 05:38 |
| wolfspra1l | they integrate some flash? | 05:38 |
| wolfspra1l | is this an area of investment or just some old chips they keep selling? | 05:38 |
| azonenberg | They're stable and not going away any time soon, but kind of a dead end | 05:44 |
| azonenberg | they're good for glue logic basically | 05:44 |
| azonenberg | super tiny (think QFN32) | 05:44 |
| azonenberg | dirt cheap, ultra-low static power | 05:45 |
| azonenberg | 22 uA typical standby current for the xc2c32a | 05:45 |
| azonenberg | 0.25 mA dynamic current at 1 MHz clock | 05:45 |
| azonenberg | Basically, you use them when an FPGA is too big | 05:46 |
| azonenberg | And they have onboard flash/eeprom so they need no external components | 05:47 |
| wolfspra1l | hmm, ok | 05:47 |
| wolfspra1l | I do believe in semiconductor economics, moores law etc | 05:47 |
| wolfspra1l | so if a chip is not receiving investment, I'd rather wait and see | 05:48 |
| azonenberg | I expect them to be EOL'd in 10 years or so | 05:48 |
| azonenberg | not sure if they plan to replace them or not | 05:48 |
| azonenberg | current xc2c is 130nm and there has been no shrink since then | 05:48 |
| wolfspra1l | most likely the 'bigger' chips are actually smaller and better, only that they sell at a higher price *because* they are better and because someone is makign a healthy profit to keep investing | 05:48 |
| wolfspra1l | which is a good thing | 05:48 |
| azonenberg | Agreed | 05:48 |
| azonenberg | xilinx is mostly pushing for high end | 05:48 |
| azonenberg | cr-ii is ultra low end | 05:48 |
| wolfspra1l | I think they push for profits, which is perfectly fine | 05:49 |
| wolfspra1l | what is 'high-end'? | 05:49 |
| azonenberg | So its not their focus but as long as they have the fab and masks | 05:49 |
| wolfspra1l | don't understand | 05:49 |
| azonenberg | and there's demand | 05:49 |
| wolfspra1l | oh of course | 05:49 |
| azonenberg | they'll keep making them | 05:49 |
| wolfspra1l | of course | 05:49 |
| azonenberg | And high end meaning high performance, lots of gates, etc | 05:49 |
| azonenberg | look at artix7 not having anything below 100k cells | 05:49 |
| wolfspra1l | which makes perfect sense | 05:49 |
| azonenberg | well on 28nm you dont want to make tiny chips | 05:50 |
| azonenberg | or your entire die is full of IOBs :P | 05:50 |
| wolfspra1l | I will stay with the slx9 for now | 05:50 |
| wolfspra1l | because it's cheap :-) | 05:50 |
| lekernel__ | wolfspraul: there's urjtag for programming FPGAs | 12:35 |
| lekernel__ | it's open source and reads bitfiles | 12:35 |
| wolfspraul | yes sure but the urjtag sources are very big and it's very difficult to trace down and fix bugs in them | 13:07 |
| lekernel__ | one big benefit is you can use any jtag cable | 13:09 |
| wolfspraul | sure I'm not against it | 13:09 |
| wolfspraul | but I ran into urjtag bugs and (trying to) fix them took me longer than to write the few things I needed myself... | 13:10 |
| lekernel__ | and I think mwalle has been pretty efficient at implementing things and getting them to work, despite the size of the source | 13:10 |
| wolfspraul | if urjtag works better for you - great | 13:10 |
| wolfspraul | perfect | 13:10 |
| lekernel__ | maybe you should report those bugs (to mwalle or whoever is responsible) | 13:10 |
| wolfspraul | hopeless case, I've moved on - but of course if urjtag works, great! | 13:11 |
| wolfspraul | just checked again - mini-jtag with just that upload thing I needed has 375 lines of .c right now | 13:11 |
| wolfspraul | three hundred | 13:12 |
| wolfspraul | urjtag... | 13:12 |
| wolfspraul | :-) | 13:12 |
| wolfspraul | 71,908 | 13:12 |
| lekernel__ | yeah but it supports a good dozen jtag cables with a thousand or so devices | 13:12 |
| wolfspraul | of course it implements hundreds of things, I'm sure | 13:12 |
| wolfspraul | wonderful | 13:12 |
| lekernel__ | of course everyone loves writing their own jtag hack :) I did that too... | 13:13 |
| wolfspraul | do you know much about high-level synthesis tools? | 13:14 |
| wolfspraul | I am reading up on legup, c-to-verilog, shang, panda, etc. | 13:14 |
| lekernel__ | yeah, I started implementing something like that in migen | 13:15 |
| lekernel__ | python subset to fhdl (and then verilog or otherwise) | 13:16 |
| wolfspraul | did you work with some of those others before? | 13:16 |
| lekernel__ | one main benefit of doing that is you can benefit from the bus/io integration to integrate your synthesized code | 13:17 |
| lekernel__ | I have used c-to-verilog, and know a (very) little about mitrion-c | 13:17 |
| lekernel__ | also tried using ORCC (CAL-to-VHDL) but it's not really usable | 13:18 |
| lekernel__ | java based, super bloated, full of bugs and crashes every 5 min | 13:18 |
| wolfspraul | ok, thanks | 13:20 |
| wolfspraul | I will look at shang a little | 13:20 |
| wolfspraul | https://github.com/OpenEDA/Shang | 13:21 |
| lekernel__ | the "modulo scheduling" paper linked from c-to-verilog is interesting | 13:21 |
| lekernel__ | wolfspraul: how are you planning to handle mapping to LUT/flip-flops and place-and-route? | 13:29 |
| wolfspraul | don't know yet | 13:42 |
| wolfspraul | i'm busy with the bits and low-level details for some more time | 13:43 |
| wolfspraul | my first test designs are all manually placed and then auto-routed with some very simple routing functions | 13:44 |
| wolfspraul | I won't start with any higher layer until a larger subset of the chip's features work | 13:44 |
| wolfspraul | right now that's maybe 1% or so ;-) | 13:44 |
| wolfspraul | no point in thinking about mapping... | 13:44 |
| kristianpaul | lekernel__: ah hi :-9 | 15:15 |
| kristianpaul | :-) | 15:15 |
| kristianpaul | lekernel__: similar situation with urjag, can you patch m1 to be compatible with any serial terminal software like screen | 15:15 |
| kristianpaul | is a shame i just can use flterm.. | 15:15 |
| kristianpaul | oops wrong channel ;) | 15:17 |
| kristianpaul | is a simple patch but the missing carriage return stops the out of the box experience with dozens of serial port terminal software out there :-) | 15:18 |
| kristianpaul | i think larsc already have a patch for it may be you can merge it to upstream with the 5bits csr as well ,) | 15:19 |
| kristianpaul | ;) | 15:19 |
| kanzure | wolfspraul: can you link me to c-to-verilog things? | 19:42 |
| kanzure | ah | 19:43 |
| --- Mon Dec 17 2012 | 00:00 | |
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