#homecmos IRC log for Sunday, 2012-12-16

--- Sun Dec 16 201200:00
kristianpaulazonenberg: http://www.bunniestudios.com/blog/?p=268604:53
azonenbergSaw it already04:53
azonenbergLooks interesting04:54
wolfspra1lazonenberg: I'm looking a bit into hls (high-level synthesis) now05:15
wolfspra1lpanda, shang, legup, c-to-verilog, fpgac, etc.05:15
azonenbergcool05:15
wolfspra1ldo you know much about that?05:15
azonenbergNo05:15
wolfspra1lI am wondering whether I should work on a llvm-backend for fpgatools05:15
azonenbergYou might want to look at xc2c* at some point05:15
wolfspra1lwhat is that?05:15
azonenbergcoolrunner-ii CPLDs05:15
azonenbergthe bitstream for the smallest device is only ~12kbits05:15
azonenbergprogramming files are ASCII and even include comments05:16
azonenbergfor which bits go to which function block etc05:16
wolfspra1lI don't know anything about those chips05:16
wolfspra1lwhy would I want to look at them?05:16
azonenbergthey're CPLDs so the microarchitecture is totally different from FPGAs05:16
azonenbergbut they're dirt cheap (like a dollar a pop)05:16
azonenbergand very simple05:16
azonenberga full toolchain would likely take a lot less time than something like xc6s05:17
azonenbergBut the downside is that since the uarch is so different from fpgas not much would port05:17
wolfspra1lwhy would I want to look at them?05:17
azonenbergBecause they're probably the easiest programmable logic in current production to make a full FOSS toolchain for05:18
wolfspra1lI know nothing about those chips so maybe it's good to learn, but I wouldn't know why right now05:18
azonenbergnot useful for much more than glue logic etc, of course05:18
azonenbergfew hundred to few thousand gate equivalents05:18
wolfspra1lthen you go and try :-)05:18
wolfspra1lwhat I see in xc6 so far is all very easy05:18
azonenbergthere's a reason i mentioned you should look ;)05:18
wolfspra1lbut what is better about those chips than say xc6slx9 ?05:19
azonenbergi'm looking into them in more depth though05:19
wolfspra1lmy current toy05:19
azonenbergOh, xc6s would be much better to have a full toolchain for in the long term05:19
wolfspra1lput the 'ease to write foss toolchain' aside for a moment05:19
wolfspra1lah ok05:19
wolfspra1lthen I shall continue there :-)05:19
azonenbergbut i think as a short-term goal if you want a FOSS programmable logic toolchain for ANYTHING05:19
azonenbergthose would be the quickest route05:19
wolfspra1lhas someone tried?05:19
azonenbergNot to my knowledge05:20
azonenbergI might look at that since there would be little overlap with fpgatools05:20
azonenbergthe microarchitecture has basically nothign in common05:20
azonenbergbut it's extremely simple05:20
wolfspra1lsure05:20
azonenbergjust a bunch of muxes and sum-of-products arrays05:20
wolfspra1lI like to first understand the quality of the chip (the hw)05:20
wolfspra1llet's assume all sw can be written05:20
azonenbergYeah05:20
azonenbergThats the thing that makes these attractive targets for study - simplicity05:20
azonenberga couple of global clocks and stuff05:20
wolfspra1lif by that comparison there is nothing or not much interesting left in xc2c*, then I'm probably not interested05:20
azonenbergIOBs05:20
azonenbergthen just logic05:20
azonenbergno multipliers, no ram, no SERDES, no memory controller05:21
wolfspra1lagain: I have done a lot of work on xc6 in the last months05:21
azonenbergYeah05:21
wolfspra1land I tell you: it's all easy05:21
azonenbergGiven where you are, you should keep going05:21
azonenbergi'll look at xc2c over the winter break if i have time05:21
wolfspra1lI will have the blinking led finished this coming week05:21
azonenberg:D05:21
wolfspra1lthen a counter with bscan-accessible register05:21
wolfspra1lthen probably some experiments with that small j1 core/soc05:21
wolfspra1lbram05:22
azonenbergalso i have (mostly) open source code working now for downloading bitstreams over jtag05:22
wolfspra1land finally I need an efficient way to program the thing, so I look into hls now05:22
azonenbergno xilinx tools needed05:22
azonenbergmostly open as in my code is bsd licensed but depends on an API that is, i think, not truly FOSS05:22
wolfspra1lsure, me too - it's included with fpgatools in the mini-jtag subdir05:22
azonenbergat least the Digilent API is not05:22
azonenbergi need to look into the FTDI api05:22
azonenbergis libftdi open?05:22
wolfspra1lcan you look at mini-jtag ? maybe there is something I can adopt from your stuff or merge?05:23
azonenbergI'll look soon05:23
azonenbergMy code isnt measnt for programming, though it has that capability05:23
azonenbergthe main point is a debug bridge for my SoC bus05:23
wolfspra1lso hls? never tried?05:23
azonenbergYeah, no experience with it05:23
wolfspra1lyou don't know these panda/shang/legup thingies?05:24
wolfspra1lok05:24
wolfspra1lazonenberg: any other news?05:31
wolfspra1lhow about the slx9 pics? :-)05:31
wolfspra1lon my side just moving forward nicely, slow though05:31
azonenbergwolfspra1l: the tungsten SEM on campus probably lacks the necessary resolutoin05:32
azonenbergi need to get trained on the FESEM05:32
azonenbergwhich happens soon05:32
azonenbergi also need to get the chip decapped, havent had time to do that either05:32
wolfspra1lnice05:32
azonenbergi have one last stack of homework to grade and then i'm done for the semester05:32
wolfspra1lI can't be that far off from finally having something that resembles a 'programmable' chip05:33
azonenbergnice05:33
wolfspra1lthough it will require months more of work05:33
wolfspra1lbut the pieces are coming together and it all works well05:33
wolfspra1lcurrently trying to finish the blinking led05:34
wolfspra1lwhich includes clock routing, more logic features than before05:34
azonenbergnice05:34
wolfspra1lthinking about the coolrunners again05:38
wolfspra1lmake the pitch - why are those chips good?05:38
wolfspra1lcheap, ok05:38
wolfspra1lthey integrate some flash?05:38
wolfspra1lis this an area of investment or just some old chips they keep selling?05:38
azonenbergThey're stable and not going away any time soon, but kind of a dead end05:44
azonenbergthey're good for glue logic basically05:44
azonenbergsuper tiny (think QFN32)05:44
azonenbergdirt cheap, ultra-low static power05:45
azonenberg22 uA typical standby current for the xc2c32a05:45
azonenberg0.25 mA dynamic current at 1 MHz clock05:45
azonenbergBasically, you use them when an FPGA is too big05:46
azonenbergAnd they have onboard flash/eeprom so they need no external components05:47
wolfspra1lhmm, ok05:47
wolfspra1lI do believe in semiconductor economics, moores law etc05:47
wolfspra1lso if a chip is not receiving investment, I'd rather wait and see05:48
azonenbergI expect them to be EOL'd in 10 years or so05:48
azonenbergnot sure if they plan to replace them or not05:48
azonenbergcurrent xc2c is 130nm and there has been no shrink since then05:48
wolfspra1lmost likely the 'bigger' chips are actually smaller and better, only that they sell at a higher price *because* they are better and because someone is makign a healthy profit to keep investing05:48
wolfspra1lwhich is a good thing05:48
azonenbergAgreed05:48
azonenbergxilinx is mostly pushing for high end05:48
azonenbergcr-ii is ultra low end05:48
wolfspra1lI think they push for profits, which is perfectly fine05:49
wolfspra1lwhat is 'high-end'?05:49
azonenbergSo its not their focus but as long as they have the fab and masks05:49
wolfspra1ldon't understand05:49
azonenbergand there's demand05:49
wolfspra1loh of course05:49
azonenbergthey'll keep making them05:49
wolfspra1lof course05:49
azonenbergAnd high end meaning high performance, lots of gates, etc05:49
azonenberglook at artix7 not having anything below 100k cells05:49
wolfspra1lwhich makes perfect sense05:49
azonenbergwell on 28nm you dont want to make tiny chips05:50
azonenbergor your entire die is full of IOBs :P05:50
wolfspra1lI will stay with the slx9 for now05:50
wolfspra1lbecause it's cheap :-)05:50
lekernel__wolfspraul: there's urjtag for programming FPGAs12:35
lekernel__it's open source and reads bitfiles12:35
wolfspraulyes sure but the urjtag sources are very big and it's very difficult to trace down and fix bugs in them13:07
lekernel__one big benefit is you can use any jtag cable13:09
wolfspraulsure I'm not against it13:09
wolfspraulbut I ran into urjtag bugs and (trying to) fix them took me longer than to write the few things I needed myself...13:10
lekernel__and I think mwalle has been pretty efficient at implementing things and getting them to work, despite the size of the source13:10
wolfspraulif urjtag works better for you - great13:10
wolfspraulperfect13:10
lekernel__maybe you should report those bugs (to mwalle or whoever is responsible)13:10
wolfspraulhopeless case, I've moved on - but of course if urjtag works, great!13:11
wolfsprauljust checked again - mini-jtag with just that upload thing I needed has 375 lines of .c right now13:11
wolfspraulthree hundred13:12
wolfspraulurjtag...13:12
wolfspraul:-)13:12
wolfspraul71,90813:12
lekernel__yeah but it supports a good dozen jtag cables with a thousand or so devices13:12
wolfspraulof course it implements hundreds of things, I'm sure13:12
wolfspraulwonderful13:12
lekernel__of course everyone loves writing their own jtag hack :) I did that too...13:13
wolfsprauldo you know much about high-level synthesis tools?13:14
wolfspraulI am reading up on legup, c-to-verilog, shang, panda, etc.13:14
lekernel__yeah, I started implementing something like that in migen13:15
lekernel__python subset to fhdl (and then verilog or otherwise)13:16
wolfsprauldid you work with some of those others before?13:16
lekernel__one main benefit of doing that is you can benefit from the bus/io integration to integrate your synthesized code13:17
lekernel__I have used c-to-verilog, and know a (very) little about mitrion-c13:17
lekernel__also tried using ORCC (CAL-to-VHDL) but it's not really usable13:18
lekernel__java based, super bloated, full of bugs and crashes every 5 min13:18
wolfspraulok, thanks13:20
wolfspraulI will look at shang a little13:20
wolfspraulhttps://github.com/OpenEDA/Shang13:21
lekernel__the "modulo scheduling" paper linked from c-to-verilog is interesting13:21
lekernel__wolfspraul: how are you planning to handle mapping to LUT/flip-flops and place-and-route?13:29
wolfsprauldon't know yet13:42
wolfsprauli'm busy with the bits and low-level details for some more time13:43
wolfspraulmy first test designs are all manually placed and then auto-routed with some very simple routing functions13:44
wolfspraulI won't start with any higher layer until a larger subset of the chip's features work13:44
wolfspraulright now that's maybe 1% or so ;-)13:44
wolfspraulno point in thinking about mapping...13:44
kristianpaullekernel__: ah hi :-915:15
kristianpaul:-)15:15
kristianpaullekernel__: similar situation with urjag, can you patch m1 to be compatible with any serial terminal software like screen15:15
kristianpaulis a shame i just can use flterm..15:15
kristianpauloops wrong channel ;)15:17
kristianpaulis a simple patch but the missing carriage return stops the out of the box experience with dozens of serial port terminal software out there :-)15:18
kristianpauli think larsc already have a patch for it may be you can merge it to upstream with the 5bits csr as well ,)15:19
kristianpaul;)15:19
kanzurewolfspraul: can you link me to c-to-verilog things?19:42
kanzureah19:43
--- Mon Dec 17 201200:00

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