| hideo | azonenberg: any hope for a cheme who last touched matlab or anything remotely close to programming to learn vhdl and fpga? | 05:37 |
|---|---|---|
| azonenberg | hideo: fpga stuff is more related to digital logic than it is programming (though it really straddles the line) | 05:37 |
| azonenberg | its a different way of thinking than conventional programming | 05:38 |
| hideo | ok so it's good that i don't have much exposure to conventional programming? | 05:38 |
| azonenberg | so its hard to say how much programming experience helps | 05:38 |
| hideo | i really have no ee background at all | 05:38 |
| azonenberg | Are you familiar with basic digital logic? | 05:38 |
| azonenberg | forget the analog stuff | 05:38 |
| hideo | like truth table? | 05:39 |
| azonenberg | boolean functions etc, the idea of clocked/synchronous vs asynchronous logic, etc | 05:39 |
| azonenberg | an FPGA is basically a big 2D grid of small RAM blocks, each one holding a truth table | 05:39 |
| hideo | i don't know the latter of what you said, sync vs. async logic | 05:40 |
| azonenberg | the size depends on the chip, for example spartan-3a is 4 inputs to one output | 05:40 |
| azonenberg | and spartan-6 is either 6 to 1, or 5 to 2 | 05:40 |
| azonenberg | (configurable on a per-block basis for whatever works best) | 05:40 |
| azonenberg | Asynchronous logic is basically raw gates | 05:40 |
| azonenberg | when the input changes, there's a short delay and then the output changes | 05:40 |
| hideo | what does raw gates mean? | 05:40 |
| azonenberg | as in, no flipflops, latches, or any kind of memory | 05:41 |
| hideo | oh ok | 05:41 |
| azonenberg | the output depends only on the input | 05:41 |
| azonenberg | at least in a simple combinational circuit | 05:41 |
| azonenberg | its possible to make asynchornous circuits that have behavior similar to memory | 05:41 |
| azonenberg | but in an FPGA you normally wont be doing that | 05:41 |
| azonenberg | So in general your design can be broken up into a bunch of logic, then a flipflop | 05:42 |
| hideo | maybe this is where i can applied my long ago learned process control class | 05:42 |
| hideo | s/applied/apply | 05:42 |
| azonenberg | You should probably move this discussion to ##electronics | 05:42 |
| azonenberg | i'm kind of busy and dont have time to talk too much now | 05:42 |
| hideo | ah it's ok | 05:42 |
| hideo | i feel dumb in there | 05:43 |
| azonenberg | lol. and you dont feel dumb here? | 05:43 |
| azonenberg | most of the stuff going on here is more advanced :P | 05:43 |
| hideo | well, litho is kinda what i do for a living | 05:43 |
| azonenberg | oh, i see | 05:43 |
| azonenberg | you work in litho process development? | 05:43 |
| hideo | i have virtually no idea what they talk about most of the time in ##electronics | 05:43 |
| azonenberg | or as a technician? | 05:43 |
| hideo | i'm a process engineer | 05:43 |
| azonenberg | ok, i see | 05:44 |
| azonenberg | where at? | 05:44 |
| hideo | see pm | 05:44 |
| --- Sat Jul 21 2012 | 00:00 | |
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