#homecmos IRC log for Tuesday, 2011-12-27

--- Tue Dec 27 201100:00
B0101hey azonenberg05:55
azonenbergBack, was visiting family for christmas20:22
azonenbergstarting up experiments again for the new year :)20:22
smedinghey, man20:23
smedingmerry belated christmas and such20:23
azonenbergty20:23
Action: smeding is doing some hardware dev of his own20:25
smedingthe laser projector project, still20:25
azonenbergvery nice20:30
azonenbergbrb20:30
wolfspra1lsmeding: another laser projector? :-)21:00
wolfspra1lI've heard of marcan's openlase project before21:00
wolfspra1ldoes yours have a homepage?21:00
azonenbergI am going to be aggressively pushing lithography resolution in the near future21:02
azonenbergi want to hit submicron21:02
azonenbergeven if only in PoC scale tests21:02
lekernelazonenberg: you should try to start with things like diffraction gratings... should be relatively easy21:05
lekerneland you can make fun ones, like those things you can put on laser pointers to project all sorts of shapes21:06
azonenberglekernel: I know21:06
azonenbergthats the goal21:06
azonenbergi want to make an optical-wavelength diffraction grating21:06
azonenbergprobably reflective21:06
azonenbergEvaporate nickel or chrome onto a bunch of microscope slides21:06
azonenbergthen do litho21:06
azonenbergI'm going to get a "real" mask as that's been my limit in the past21:07
lekernelwhat materials do they use for the laser pointer thingies?21:07
lekernelwould be fun to make your own21:07
azonenbergsend the GDS over to a place like laserlab and have them send me 8000DPI film masks21:07
azonenbergThat will give me 12.5um design rules and a 3.125um lambda21:08
azonenbergTimes 4/10/40x reduction with my objectives21:08
azonenbergshould be easily enough to hit submicron21:08
azonenbergI do question whether 12.5um might be too small to resolve on the mask side, i might have to make my design rule be more like 25 or 5021:08
azonenbergBut there's only one way to find out21:08
azonenbergThe mask will cost me around $100 and be 10x16 inches usable area21:09
azonenbergso i'm gonna tile a mix of 2" contact masks and projection masks of various feature sizes21:09
azonenbergincluding test patterns and probably some comb drive stuff21:09
smedingwolfspra1l: nope, mine mostly doesn't exist yet21:22
smedingmight not even bother with building the hardware21:22
smedingmy UART for it won't work though :(21:23
smedingi'm writing VHDL, it's to familiarise myself with digital signal processing more21:25
azonenbergi see21:26
azonenbergAnd yeah a UART is a little slow for that kind of bandwidth21:26
azonenbergyou'd be better off with USB21:26
azonenbergand ideally, feed the GDS into the FPGA over USB and have it do rasterization onboard21:26
azonenbergso as to avoid the 480Mbps bottleneck21:26
azonenbergOf course at that point you're basically writing a 2D GPU21:27
azonenbergWhich is, to say the least, a nontrivial task21:27
smedingeh, i'm not going for many points/second at first21:29
smedingit will be a vector display21:29
azonenbergOh21:29
azonenbergSo you rent doing it for direct-write litho?21:29
smedingeh? this is just for playing21:29
smeding:p21:29
azonenbergarent*21:29
smedingnonono21:29
smedingthis is pretty much a toy21:29
azonenbergBecause i want to build a laser system using a bluray diode for doing lithography lol21:29
smedingi doubt you can use my code :p21:30
azonenberglol21:30
smedingthis is kind of the wrong channel for it, i suppose21:30
smedingbut yeah, it's a toy -- PID loops in digital hardware to drive two galvos to scan a laser beam21:31
azonenbergI see21:31
azonenbergI'd be doing basically the same thing21:31
azonenbergExcept trying for much higher tolerances21:31
azonenbergso i can get ~20 micron resolution21:31
azonenbergMight need some optics but we'll see21:31
smedingyeah, nice21:31
smedingthis is just my foray into tinkering with DSP21:31
smedingi'm not quite sure how to do the actual control loop yet... i wrote the dinky motor driver and ADC readout modules21:32
azonenbergi see21:32
azonenbergI'm going to try for tens of MHz data rate if not better21:32
azonenbergideally more like 10021:32
azonenbergas in 100Mpps21:32
azonenbergwhich, on a scanning apparatus, should let me cover a small field (1cm^2) in a decent time21:33
smedingthen i wrote a FIFO and now i'm working on a UART to hook to that21:33
azonenbergi see21:33
smedingthen, the PID controller and the main controller that loads points from memory and presents them to the control loops21:33
smedingand can write from the uart-fifo to memory21:33
smedingbut currently i have a silly error in my VHDL somewhere, but i can't see where and ISim won't tell me21:34
azonenberghow so?21:35
smedingit just tells me what VHDL process is in21:35
smedingit's the process that generates the new state data for the sort-of-state-machine21:35
smedingwell, state machine, but not evidently so21:35
smedingit's pretty big (and probably inefficient)21:35
azonenbergIf you want to see a nice simple uart in verilog, i wrote one i use in a couple of projects21:36
azonenbergno fifo, this is just the raw uart21:36
smedingi should have one in VHDL somewhere21:36
smedingbut where's the fun in that21:36
azonenbergIt's <200 lines21:36
smedingyeah so's this21:36
smeding123 lines21:36
azonenbergMine is 193 but pretty heavy commenting21:37
azonenberghttp://pastebin.com/9rxLMFHS21:37
azonenbergIt's also instrumented to log bytes to the console21:37
azonenbergSo if you want to compare the two and see where they differe feel free21:38
azonenbergthis is FPGA proven in a spartan-3a at 20.48 MHz while talking to an FT23221:38
azonenbergat 115200 baud21:38
smedingoh, mine is just the rx side actually21:39
azonenbergWell this plays fine in TX mode too if you want to generate a waveform to test against21:40
smedingand probably overly complicated21:40
azonenbergYours or mine?21:40
smedingmine21:40
smedingyours seems sane enough21:40
azonenbergMine is pretty simple, the one complex feature i added was samplnig 90 degrees out of phase21:40
azonenbergto avoid any settling issues on the signal edge21:40
smedingyeah21:40
azonenbergi instead wait half a bit period21:40
smedingmine samples thrice21:41
smedingand does best of 321:41
azonenbergThats the alternate option21:41
smedingi felt like overcomplicating21:41
azonenbergalso, mine allows runtime changing of baud rate21:41
smedingneat21:42
azonenbergthough i usually synthesize it with a constant since i dont need to change it21:42
azonenbergand it optimizes out a few gates21:42
smedingi'll brb21:42
smedinghave to walk the dog21:42
azonenbergBut theoretically as long as clkdiv does not change while a character is on the wire (in either direction) it should handle changing fine21:42
smedingback22:02
smedingactually i had been for a while22:02
--- Wed Dec 28 201100:00

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