#homecmos IRC log for Thursday, 2011-09-29

Action: mrdata wants to make artificial neurons17:42
azonenberg_workmrdata: how so?17:42
mrdatai was thinking that a neuron is like a generic gate with a resistor network17:43
azonenberg_worki dont know neurology enough to know how they work lol17:43
mrdatawhere the resistor values can be modified17:43
mrdatabasically, an axon fires when its chemical potential reaches a threshold; but synapses can enhance of inhibit this17:44
mrdataso analogously, a transistor will non-linearly amplify its inputs; the resistor network simulates the synapses17:45
mrdata^^ synapses enhance *or* inhibit, that is17:46
mrdataso, each generic gate generates a pulse when it fires; a transistor with a small capacitor on its output can do that17:47
mrdataand, neurons tend to fire spontaneously also; so pulse rate and timing is probably the more significant17:48
azonenberg_workhmm17:49
azonenberg_workI know there is work being done in the field but i'm not familiar with it myself17:49
mrdatai've read a few papers; most are either attempting to simulate artificial neurons in large AI frameworks in lisp, or studying precise behaviour of real life neurons in microbiological sense17:51
azonenberg_worki see17:52
mrdatabut i havent seen attempts to build programmable gate arrays, of them yet17:52
azonenberg_workSo you want to build an FPGA-like programmable brain?17:52
mrdatathat would be nice17:52
mrdatathe problem is, the connections architecture, which is of crucial significance, is unknown17:53
mrdatabut, if the thing i build can be a physical manifestation of some of the artificial neural networks made with genetic algorithms, then the connections architecture can be decided by the genetic algorithms17:54
azonenberg_workVery interesting17:55
mrdatathe important step will be, how to adequately represent the behaviour, both in an FPGA, and in a simulator17:55
mrdataso that they map17:55
azonenberg_worknot sure if its possible in an fpga17:56
azonenberg_workthis project sounds analog17:56
mrdatahomecmos to the rescue17:57
mrdatagoal: build and make scalable artificial neurons17:57
azonenberg_worklol19:23
azonenberg_workWorthy goal, just not an easy one19:23
mrdataindeed19:24
mrdatabut this was predicted to occur; and so it should be done19:24
Action: mrdata would be satisfied with a network of half a dozen axons, to start19:25
mrdatawith re-programmable connections and strengths19:25
azonenberg_workYou're probably talking a couple hundred transistors19:26
azonenberg_workdefinitely possible but at least a year out19:27
mrdatawhy not 6 transistors?19:33
azonenberg_workI'm assuming you will need a few more than that in order to amplify inputs19:34
cheaterit's that simple only if you don't model channeling, receptors, etc19:34
azonenberg_workand act as resistors19:34
azonenberg_workthen programmable drive strength will be a task in itself19:34
azonenberg_workprobably means having four or five transistors that you can turn on one, two, three, four, or all19:34
azonenberg_workhooked up in parallel19:35
azonenberg_workAnd in any case i have yet to make even one working transistor19:35
azonenberg_worki havent even attemptd them as my MEMS focus has kept me from buying the materials19:35
Action: mrdata bets each synapse is a small capacitor and resistor; and a single axon will have no more than 2 transistors19:36
azonenberg_workbut a variable resistor or a fixed?19:37
mrdatasince a not gate is modeled as a single NPN19:37
azonenberg_workand if you are doing cmos, remember you need two for everything as a push-pull19:37
azonenberg_workyou generally cannot drive high and low with a single transistor19:38
mrdatathe resistor and/or the capacitor may be variable19:38
azonenberg_workvariable caps are highly nontriial19:38
azonenberg_worknontrivial*19:38
azonenberg_workvariable resistors a bit less so, you have a big resistive element and transistors to short out each segment on request19:38
mrdataok, i imagine fixed capacitance will do19:39
mrdatabut R must be variable19:39
mrdatacan be quantized19:39
mrdatato about 250 or so values19:39
azonenberg_work256? You can do that with whats basically an 8 bit DAC19:40
azonenberg_workor digital port19:40
mrdataok19:40
azonenberg_workpot*19:40
azonenberg_workyou have a N/2 ohm segment you can short out when r[7] is low19:41
azonenberg_workan N/4 ohm segment you short when r[6] is low19:41
azonenberg_workup to an n/256 ohm segment you short when r[0] is low19:41
azonenberg_workso eight transistors and eight resistive elements19:41
mrdataok, so each neuron becomes a couple transistors for the axon, and an 8-bit DAC, and stuff, for each synapse19:41
azonenberg_workplus latches for each transistor to hold the on/off state19:41
azonenberg_workyou are looking at eight switching transistors, eight D flipflops, and an 8-segment resistor19:42
mrdataok. latched19:42
azonenberg_workor atlternatively, a sample-and-hold circuit (analog flipflop, pretty much)19:42
azonenberg_workand eight comparators19:42
azonenberg_workgoing to the transsitors19:42
azonenberg_workthat way you can control the resistance by an analog input19:42
azonenberg_workYou might even be able to have the S&H output go straight to the gate of a transistor operated inthe linerar region19:43
azonenberg_worklinear*19:43
azonenberg_workand use it as the resistive element19:43
azonenberg_workthat'd probably be the best option19:43
azonenberg_workSo you have a capacitor, some kind of feedback circuit that compensates exactly for leakage by recharging as it leaks19:44
azonenberg_workand a single transistor19:44
azonenberg_workto form your latchable variable resistor19:44
azonenberg_workthen one more transistor connecting your control input to the capacitor so you can charge or discharge it on demand19:44
mrdataand all these are in simplest possible elements that can be printed onto a die19:46
azonenberg_worktransistors are easy, caps arent bad19:46
azonenberg_worknot sure how the sample-and-hold works19:47
mrdatain real life, there are many synapses for each axon; 100:1 may be common19:49
mrdatabut in a small device of half a dozen, full connection is 6:1 (including back-propagation)19:50
mrdataand these values should be brought to output. so about 6 inputs, 36 outputs, and some lines to program it19:54
azonenberg_worklol yes, that will be nontrivial to construct19:56
azonenberg_workVery interesting research project for sure19:56
azonenberg_workBut my process is a couple years from being able to build it i think19:57
mrdatanoted19:59
mrdatai will try breadboarding it first, ithink19:59
mrdatajust to verify the circuitry on a small scale20:00
mrdatait will be important for the simulator to give pretty-close to identical results to the physical device20:00
mrdataotherwise the connections architecture cant be evolved20:01
azonenberg_workYou will likely have to train on the physical hardware20:02
mrdatayes20:02
azonenberg_workespecially if using a homebrew process with lots of variation between parts20:02
azonenberg_workthe device's little variations will become almost a part of the program20:03
mrdatai expect they will, yes20:03
mrdataso, so long as the variations are "small enough" that they may be compensated-for with minor training, the connections architecture will be common to both simulator and physical device20:04
azonenberg_workWell, i suggest that you test it out on a breadboard because its quite a ways from being IC-able20:04
azonenberg_workat least on my process20:04
azonenberg_workI'd love to see results20:04
mrdatasure. i can throw these ideas into a circuit simulator even before that20:05
mrdataeven before i spend $ on parts20:06
azonenberg_workyep20:06
mrdatacant promise timing, but i have some time before xmas20:07
mrdataa bunch of these might be what i need http://www.analog.com/static/imported-files/data_sheets/AD5200_5201.pdf20:28
--- Fri Sep 30 201100:00

Generated by irclog2html.py 2.9.2 by Marius Gedminas - find it at mg.pov.lt!