| reportingsjr | azonenberg: are you still working on your vhdl cpu? | 21:33 |
|---|---|---|
| reportingsjr | or is that kaput | 21:33 |
| lekernel | reportingsjr, check out www.milkymist.org. we are taking care of *HDL CPUs so azonenberg can focus on doing great stuff with chemistry and DIY semiconductor manufacturing ;-) | 21:35 |
| reportingsjr | haha | 21:37 |
| reportingsjr | will do | 21:37 |
| reportingsjr | ohhh yeah, I saw that website a while ago | 21:37 |
| reportingsjr | and I just saw it mentioned somewhere else a few days ago | 21:38 |
| reportingsjr | on the adafruit forums for x0xb0x | 21:38 |
| bart416 | So we need to design a CPU so azonenberg can do other stuff? | 21:44 |
| bart416 | Can do | 21:44 |
| bart416 | Have another set of boring VHDL classes and labs anyway next semester | 21:44 |
| lekernel | well, azonenberg's process is still far from making CPUs | 21:48 |
| lekernel | and it'll probably start by making things like 4004 or 6502 chips before synthesized VHDL | 21:48 |
| reportingsjr | bart416: I had my first verilog/fpga class last quarter. Was digital logic first half was with 74 series stuff and second half was fpga stuff. | 21:50 |
| reportingsjr | I almost prefer the 74 series stuff. We weren't really taught how to use the provided program and it was terrible for beginners | 21:52 |
| bart416 | lekernel, please note the "another" :P | 21:54 |
| bart416 | The reason we're forced to take it is cause we have microcontroller design as well at the same time | 21:54 |
| reportingsjr | bart416: are you CE? | 22:14 |
| bart416 | No | 22:14 |
| bart416 | EE | 22:14 |
| bart416 | well, studying for EE | 22:14 |
| bart416 | The only degree I hold at this point is bachelor in physics | 22:14 |
| azonenberg | reportingsjr: its verilog | 22:37 |
| azonenberg | (my cpu) | 22:37 |
| bart416 | Eeeeewy | 22:37 |
| --- Fri Aug 19 2011 | 00:00 | |
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